| Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design S Mahapatra, V Vaish, C Wasshuber, K Banerjee, AM Ionescu IEEE Transactions on Electron Devices 51 (11), 1772-1782, 2004 | 218 | 2004 |
| Drive current boosting of n-type tunnel FET with strained SiGe layer at source N Patel, A Ramesha, S Mahapatra Microelectronics Journal 39 (12), 1671-1677, 2008 | 147 | 2008 |
| Monolayer transition metal dichalcogenide channel-based tunnel transistor RK Ghosh, S Mahapatra IEEE Journal of the electron devices society 1 (10), 175-180, 2013 | 117 | 2013 |
| Hybrid CMOS single-electron-transistor device and circuit design S Mahapatra, AM Ionescu Artech House, Inc., 2006 | 105 | 2006 |
| Realization of multiple valued logic and memory by hybrid SETMOS architecture S Mahapatra, AM Ionescu IEEE transactions on Nanotechnology 4 (6), 705-714, 2005 | 104 | 2005 |
| High-throughput discovery of high Curie point two-dimensional ferromagnetic materials A Kabiraj, M Kumar, S Mahapatra npj Computational Materials 6 (1), 35, 2020 | 97 | 2020 |
| A quasi-analytical SET model for few electron circuit simulation S Mahapatra, AM Ionescu, K Banerjee IEEE Electron device letters 23 (6), 366-368, 2002 | 90 | 2002 |
| Few electron devices: towards hybrid CMOS-SET integrated circuits AM Ionescu, MJ Declercq, S Mahapatra, K Banerjee, J Gautier Proceedings of the 39th annual Design Automation Conference, 88-93, 2002 | 75 | 2002 |
| Modeling of channel potential and subthreshold slope of symmetric double-gate transistor B Ray, S Mahapatra IEEE Transactions on Electron Devices 56 (2), 260-266, 2009 | 71 | 2009 |
| Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive AM Ionescu, S Mahapatra, V Pott IEEE Electron Device Letters 25 (6), 411-413, 2004 | 60 | 2004 |
| Modelling and analysis of power dissipation in single electron logic S Mahapatra, AM Ionescu, K Banerjee, MJ Declercq Digest. International Electron Devices Meeting,, 323-326, 2002 | 52 | 2002 |
| Germanane: A low effective mass and high bandgap 2-D channel material for future FETs RK Ghosh, M Brahma, S Mahapatra IEEE Transactions on Electron Devices 61 (7), 2309-2315, 2014 | 48 | 2014 |
| A computationally efficient generalized Poisson solution for independent double-gate transistors A Sahoo, PK Thakur, S Mahapatra IEEE transactions on electron devices 57 (3), 632-636, 2010 | 48 | 2010 |
| Atomistic modeling of the metallic-to-semiconducting phase boundaries in monolayer MoS2 D Saha, S Mahapatra Applied Physics Letters 108 (25), 2016 | 45 | 2016 |
| Modeling and analysis of body potential of cylindrical gate-all-around nanowire transistor B Ray, S Mahapatra IEEE Transactions on Electron Devices 55 (9), 2409-2416, 2008 | 44 | 2008 |
| Analytical insight into the lattice thermal conductivity and heat capacity of monolayer MoS2 D Saha, S Mahapatra Physica E: Low-dimensional Systems and Nanostructures 83, 455-460, 2016 | 43 | 2016 |
| Photo-tunable transfer characteristics in MoTe2–MoS2 vertical heterostructure AK Paul, M Kuiri, D Saha, B Chakraborty, S Mahapatra, AK Sood, A Das npj 2D Materials and Applications 1 (1), 17, 2017 | 42 | 2017 |
| Prospects of zero Schottky barrier height in a graphene-inserted MoS2-metal interface A Chanana, S Mahapatra Journal of Applied Physics 119 (1), 2016 | 42 | 2016 |
| A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits S Mahapatra, K Banerjee, F Pegeon, AM Ionescu ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 41 | 2003 |
| Performance Analysis of Strained Monolayer MoS₂ MOSFET A Sengupta, RK Ghosh, S Mahapatra IEEE Transactions on Electron Devices 60 (9), 2782-2787, 2013 | 40 | 2013 |
