Pushing the limits of energy efficiency for non-binary LDPC decoders on GPUs and FPGAs S Subramaniyan, O Ferraz, MR Ashuthosh, S Krishna, G Wang, ... 2020 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2020 | 3 | 2020 |
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders S Subramaniyan, O Ferraz, MR Ashuthosh, S Krishna, G Wang, ... IEEE Design & Test, 2022 | 1 | 2022 |
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication MR Ashuthosh, S Krishna, V Sudarshan, S Subramaniyan, M Purnaprajna 2022 35th International Conference on VLSI Design and 2022 21st …, 2022 | | 2022 |
Best Paper Awards MR Ashuthosh, S Krishna, V Sudarshan, S Subramaniyan, M Purnaprajna, ... | | |