| A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards S Shen, W Shen, Y Fan, X Zeng 2012 IEEE International Conference on Multimedia and Expo, 788-793, 2012 | 80 | 2012 |
| A high-throughput VLSI architecture for deblocking filter in HEVC W Shen, Q Shang, S Shen, Y Fan, X Zeng 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 673-676, 2013 | 52 | 2013 |
| Single-port SRAM-based transpose memory with diagonal data mapping for large size 2-D DCT/IDCT Q Shang, Y Fan, W Shen, S Shen, X Zeng IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (11 …, 2014 | 33 | 2014 |
| A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC S Shen, W Shen, Y Fan, X Zeng IEICE Electronics Express 10 (11), 20130272-20130272, 2013 | 19 | 2013 |
| A unified forward/inverse transform architecture for multi-standard video codec design S Shen, W Shen, Y Fan, X Zeng IEICE Transactions on Fundamentals of Electronics, Communications and …, 2013 | 11 | 2013 |
| uClinux 操作系统在嵌入式 SOC 平台上的移植 沈沙， 苏佳宁， 田骏骅， 章倩苓 计算机工程与应用 40 (26), 104-105, 2004 | 6 | 2004 |
| 一种带有流水线追踪器的 JTAG ICE 调试电路设计 沈沙， 沈泊， 章倩苓 微电子学与计算机 21 (7), 139-142, 2004 | 5 | 2004 |
| A 4-way parallel CAVLC design for H. 264/AVC 4Kx2K 60fps encoder H Zhong, S Shen, Y Fan, X Zeng IEICE Electronics Express 8 (22), 1863-1869, 2011 | 3 | 2011 |
| A low complexity macroblock layer rate control scheme base on weighted-window for h. 264 encoder H Zhong, S Shen, Y Fan, X Zeng Advances in Multimedia Modeling: 18th International Conference, MMM 2012 …, 2012 | 2 | 2012 |
| A two-way parallel CAVLC encoder for 4K× 2K H. 264/AVC H Zhong, S Shen, Y Fan, X Zeng 2011 9th IEEE International Conference on ASIC, 75-78, 2011 | 2 | 2011 |
| A hardware/software co-design approach for multiple-standard video bitstream parsing S Shen, H Zhong, Y Fan, X Zeng 2011 9th IEEE International Conference on ASIC, 43-46, 2011 | | 2011 |
