| Design and analysis of analog performance of dual-k spacer underlap N/P-FinFET at 12 nm gate length A Nandi, AK Saxena, S Dasgupta IEEE transactions on electron devices 60 (5), 1529-1535, 2013 | 75 | 2013 |
| Comparative study of 16‐order FIR filter design using different multiplication techniques A Mittal, A Nandi, D Yadav IET Circuits, Devices & Systems 11 (3), 196-200, 2017 | 73 | 2017 |
| Analytical modeling of a double gate MOSFET considering source/drain lateral Gaussian doping profile A Nandi, AK Saxena, S Dasgupta IEEE Transactions on Electron Devices 60 (11), 3705-3709, 2013 | 64 | 2013 |
| Analog/RF performance analysis of channel engineered high-k gate-stack based junctionless trigate-FinFET S Tayal, A Nandi Superlattices and Microstructures 112, 287-295, 2017 | 63 | 2017 |
| Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications S Tayal, A Nandi Materials Science in Semiconductor Processing 80, 63-67, 2018 | 43 | 2018 |
| Analog/RF performance analysis of inner gate engineered junctionless Si nanotube S Tayal, A Nandi Superlattices and Microstructures 111, 862-871, 2017 | 40 | 2017 |
| Impact of dual-k spacer on analog performance of underlap FinFET A Nandi, AK Saxena, S Dasgupta Microelectronics Journal 43 (11), 883-887, 2012 | 38 | 2012 |
| Modeling of Short-Channel Effects in DG MOSFETs: Green's Function Method Versus Scale Length Model N Pandey, HH Lin, A Nandi, Y Taur IEEE Transactions on Electron Devices 65 (8), 3112-3119, 2018 | 34 | 2018 |
| Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET S Tayal, A Nandi Superlattices and Microstructures 105, 152-162, 2017 | 34 | 2017 |
| Enhancing low temperature analog performance of underlap FinFET at scaled gate lengths A Nandi, AK Saxena, S Dasgupta IEEE Transactions on Electron Devices 61 (11), 3619-3624, 2014 | 33 | 2014 |
| Effect of air spacer on analog performance of underlap tri-gate FinFET S Gupta, A Nandi Superlattices and Microstructures 109, 693-701, 2017 | 29 | 2017 |
| Study of 6T SRAM cell using high-k gate dielectric based junctionless silicon nanotube FET S Tayal, A Nandi Superlattices and Microstructures 112, 143-150, 2017 | 28 | 2017 |
| Analytical modeling of DG-MOSFET in subthreshold regime by green’s function approach A Nandi, N Pandey, S Dasgupta IEEE Transactions on Electron Devices 64 (8), 3056-3062, 2017 | 28 | 2017 |
| A comprehensive investigation of vertically stacked silicon nanosheet field effect transistors: an analog/rf perspective S Tayal, J Ajayan, LMIL Joseph, J Tarunkumar, D Nirmal, B Jena, A Nandi Silicon 14 (7), 3543-3550, 2022 | 27 | 2022 |
| Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance S Tayal, A Nandi Cryogenics 92, 71-75, 2018 | 21 | 2018 |
| Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration S Tayal, A Nandi Micro & Nano Letters 13 (6), 838-841, 2018 | 19 | 2018 |
| Accurate analytical modeling of junctionless DG-MOSFET by green's function approach A Nandi, N Pandey Superlattices and Microstructures 111, 983-990, 2017 | 19 | 2017 |
| Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective S Tayal, V Mittal, S Jadav, S Gupta, A Nandi, B Krishan Cryogenics 108, 103087, 2020 | 18 | 2020 |
| Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM S Tayal, A Nandi Micro & Nano Letters 13 (7), 965-968, 2018 | 18 | 2018 |
| Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET A Nandi, AK Saxena, S Dasgupta Microelectronics journal 55, 19-25, 2016 | 18 | 2016 |
Shubham TayalSynopsys India Pvt. Ltd., Hyderabad在 nitkkr.ac.in 的电子邮件经过验证
