| ePlace: Electrostatics-based placement using fast fourier transform and Nesterov's method J Lu, P Chen, CC Chang, L Sha, DJH Huang, CC Teng, CK Cheng ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (2 …, 2015 | 129 | 2015 |
| ePlace-MS: Electrostatics-based placement for mixed-size circuits J Lu, H Zhuang, P Chen, H Chang, CC Chang, YC Wong, L Sha, D Huang, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 97 | 2015 |
| ePlace: Electrostatics based placement using Nesterov's method J Lu, P Chen, CC Chang, L Sha, DJH Huang, CC Teng, CK Cheng Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 67 | 2014 |
| ePlace-3D: Electrostatics based placement for 3D-ICs J Lu, H Zhuang, I Kang, P Chen, CK Cheng Proceedings of the 2016 on International Symposium on Physical Design, 11-18, 2016 | 48 | 2016 |
| Fast power-and slew-aware gated clock tree synthesis J Lu, WK Chow, CW Sham IEEE Transactions on very large scale integration (VLSI) Systems 20 (11 …, 2011 | 41 | 2011 |
| LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search J Lu, CW Sham International Symposium on Quality Electronic Design (ISQED), 231-238, 2013 | 24 | 2013 |
| A new clock network synthesizer for modern vlsi designs J Lu, WK Chow, CW Sham Integration 45 (2), 121-131, 2012 | 24 | 2012 |
| A dual-MST approach for clock network synthesis J Lu, WK Chow, CW Sham, EFY Young 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 467-473, 2010 | 24 | 2010 |
| Congestion prediction in early stages of physical design CW Sham, EFY Young, J Lu ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (1 …, 2009 | 23 | 2009 |
| FFTPL: An analytic placement algorithm using fast fourier transform for density equalization J Lu, P Chen, CC Chang, L Sha, DJH Huang, CC Teng, CK Cheng 2013 IEEE 10th International Conference on ASIC, 1-4, 2013 | 16 | 2013 |
| Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs H Zhuang, J Lu, K Samadi, Y Du, CK Cheng 2013 International Conference on Communications, Circuits and Systems …, 2013 | 12 | 2013 |
| Stability and scalability in global routing SK Han, K Jeong, AB Kahng, J Lu International Workshop on System Level Interconnect Prediction, 1-6, 2011 | 9 | 2011 |
| Fundamental research on electronic design automation in VLSI design: Routability J Lu Hong Kong Polytechnic University, 2010 | 9 | 2010 |
| Worst-case noise area prediction of on-chip power distribution network X Zhang, J Lu, Y Liu, CK Cheng Proceedings of SLIP (System Level Interconnect Prediction) on System Level …, 2014 | 5 | 2014 |
| Clock network synthesis with concurrent gate insertion J Lu, WK Chow, CW Sham Integrated Circuit and System Design. Power and Timing Modeling …, 2011 | 4 | 2011 |
| Analytic VLSI Placement using Electrostatic Analogy J Lu University of California, San Diego, 2014 | 1 | 2014 |
| CSE 20 Discrete Mathematics J Lu, R Motta | | |
