| FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template NK Choudhary, SV Wadhavkar, TA Shah, H Mayukh, J Gandhi, BH Dwiel, ... ACM SIGARCH Computer Architecture News 39 (3), 11-22, 2011 | 195 | 2011 |
| Fabscalar: Automating superscalar core design N Choudhary, S Wadhavkar, T Shah, H Mayukh, J Gandhi, B Dwiel, ... IEEE Micro 32 (3), 48-59, 2012 | 44 | 2012 |
| Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor A Krishna, RW Smith, SS Navada, S Priyadarshi, R Damodaran US Patent 10,108,417, 2018 | 40 | 2018 |
| A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors S Navada, NK Choudhary, SV Wadhavkar, E Rotenberg Proceedings of the 22nd international conference on Parallel architectures …, 2013 | 35 | 2013 |
| Fabscalar NK Choudhary, SV Wadhavkar, TA Shah, H Mayukh, J Gandhi, BH Dwiel, ... ACM SIGARCH Computer Architecture News 39 (3), 11-22, 2011 | 23 | 2011 |
| Criticality-driven superscalar design space exploration S Navada, NK Choudhary, E Rotenberg Proceedings of the 19th international conference on Parallel architectures …, 2010 | 17 | 2010 |
| Hierarchical register file system A Krishna, RW Smith, SS Navada, S Priyadarshi, NK Choudhary, ... US Patent App. 14/843,921, 2017 | 13 | 2017 |
| Method and apparatus for selective renaming in a microprocessor A Krishna, SS Navada, NK Choudhary, MS McIlvaine, TA Sartorius, ... US Patent 9,471,325, 2016 | 12 | 2016 |
| An exploration of opencl for a numerical relativity application NK Choudhary, R Ginjupalli, S Navada, G Khanna arXiv preprint arXiv:1010.3816, 2010 | 7 | 2010 |
| Hypervector-based branch prediction SS Navada US Patent App. 15/587,371, 2017 | 6 | 2017 |
| Physical register scrubbing in a computer microprocessor A Krishna, W Wu, SS Navada, NK Choudhary, RW Smith US Patent App. 14/221,430, 2015 | 6 | 2015 |
| A Unified View of Core Selection and Application Steering in Heterogeneous Chip Multiprocessors SS Navada North Carolina State University, 2012 | 6 | 2012 |
| Branch target instruction cache (btic) to store a conditional branch instruction NK Choudhary, MS McIlvaine, DE Streett, VK Reddy, SS Srikantaiah, ... US Patent App. 14/859,356, 2017 | 3 | 2017 |
| Providing early pipeline optimization of conditional instructions in processor-based systems SS Navada, MS McIlvaine, RW Smith, RD Clancy, YC Tekmen, ... US Patent App. 15/926,429, 2019 | | 2019 |
| Criticality Aware Multiprocessors S Navada, A Krishna arXiv preprint arXiv:1606.05933, 2016 | | 2016 |
| 3 Guest Editors’ Introduction: Top Picks from the 2011 Computer Architecture Conferences Paolo Faraboschi and TN Vijaykumar 7 Kilo TM: Hardware Transactional Memory for GPU … WWL Fung, I Singh, A Brownsword, TM Aamodt, B Grot, J Hestness, ... | | 2012 |
| 1. FabScalar: Motivation and Concept NK Choudhary, SV Wadhavkar, TA Shah, SS Navada, HH Najaf-abadi, ... | | |
