| Design and Analysis of a New Ultra Low Power Adiabatic VLSI Circuit C Ganguly, SH Rakib, FT Aumio, A Islam, SK Kabir, R Motalib, SN Biswas Journal of VLSI Design and Signal Processing, 1-12, 2023 | 2 | 2023 |
| Analysis of a Low-Power Full Adder and Half Adder Using a New Adiabatic Logic C Ganguly, MZ Meem, SMK Kabir, SN Biswas 2023 26th International Conference on Computer and Information Technology …, 2023 | | 2023 |
| Analysis of a 10T Full Adder with a new 4T X-NOR using FD-SOI 22nm Mix-VT Technology SMK Kabir, C Ganguly, KS Arefin, NT Adity, SN Biswas 2023 26th International Conference on Computer and Information Technology …, 2023 | | 2023 |
| Performance Evaluation and Comparative Analysis of Logic Gates based on CNTFET and CMOS R Redwan, C Ganguly, SS Islam, MF Nayan 2023 26th International Conference on Computer and Information Technology …, 2023 | | 2023 |
| Comparative Analysis of a Proposed Low-Power Adiabatic NOR Gate C Ganguly, MZ Meem, MA Faruque, SMK Kabir, SH Rakib, KS Arefin 2023 26th International Conference on Computer and Information Technology …, 2023 | | 2023 |
| Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors SMK Kabir, R Motalib, FI Javed, C Ganguly, SH Rakib, SN Biswas 2023 6th International Conference on Electrical Information and …, 2023 | | 2023 |
S.M Kifayat KabirMemory Design Engineer, ULKASEMI在 ulkasemi.com 的电子邮件经过验证
