| A novel threshold voltage defined switch for circuit camouflaging IR Nirmala, D Vontela, S Ghosh, A Iyengar 2016 21th IEEE European Test Symposium (ETS), 1-2, 2016 | 49 | 2016 |
| DWM-PUF: A low-overhead, memory-based security primitive A Iyengar, K Ramclam, S Ghosh 2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014 | 40 | 2014 |
| Modeling and analysis of domain wall dynamics for robust and low-power embedded memory A Iyengar, S Ghosh Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 37 | 2014 |
| MTJ-based state retentive flip-flop with enhanced-scan capability to sustain sudden power failure AS Iyengar, S Ghosh, JW Jang IEEE Transactions on Circuits and Systems I: Regular Papers 62 (8), 2062-2068, 2015 | 36 | 2015 |
| Data privacy in non-volatile cache: Challenges, attack models and solutions N Rathi, S Ghosh, A Iyengar, H Naeimi 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 348-353, 2016 | 30 | 2016 |
| Domain wall memory-layout, circuit and synergistic systems S Motaman, AS Iyengar, S Ghosh IEEE Transactions on Nanotechnology 14 (2), 282-291, 2015 | 29 | 2015 |
| Synergistic circuit and system design for energy-efficient and robust domain wall caches S Motaman, A Iyengar, S Ghosh Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 27 | 2014 |
| Domain wall magnets for embedded memory and hardware security AS Iyengar, S Ghosh, K Ramclam IEEE journal on emerging and selected topics in circuits and systems 5 (1 …, 2015 | 25 | 2015 |
| Side channel attacks on STTRAM and low-overhead countermeasures A Iyengar, S Ghosh, N Rathi, H Naeimi 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2016 | 24 | 2016 |
| Threshold voltage-defined switches for programmable gates A Iyengar, S Ghosh arXiv preprint arXiv:1512.01581, 2015 | 23 | 2015 |
| Spintronic PUFs for security, trust, and authentication A Iyengar, S Ghosh, K Ramclam, JW Jang, CW Lin ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (1), 1-15, 2016 | 19 | 2016 |
| Retention testing methodology for STTRAM A Iyengar, S Ghosh, S Srinivasan IEEE Design & Test 33 (5), 7-15, 2016 | 15 | 2016 |
| Novel magnetic burn-in for retention testing of STTRAM MNI Khan, AS Iyengar, S Ghosh Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 14 | 2017 |
| Threshold defined camouflaged gates in 65nm technology for reverse engineering protection AS Iyengar, D Vontela, I Reddy, S Ghosh, S Motaman, J Jang Proceedings of the International Symposium on Low Power Electronics and …, 2018 | 12 | 2018 |
| Overview of circuits, systems, and applications of spintronics S Ghosh, A Iyengar, S Motaman, R Govindaraj, JW Jang, J Chung, J Park, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (3 …, 2016 | 11 | 2016 |
| Hardware trojans and piracy of PCBs A Iyengar, S Ghosh The hardware Trojan war: Attacks, myths, and defenses, 125-145, 2018 | 9 | 2018 |
| Novel magnetic burn-in for retention and magnetic tolerance testing of STTRAM MNI Khan, AS Iyengar, S Ghosh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (8 …, 2018 | 8 | 2018 |
| Physically unclonable function based on domain wall memory and method of use S Ghosh, AS Iyengar, K Ramclam US Patent 9,859,018, 2018 | 8 | 2018 |
| Design space exploration for selector diode-STTRAM crossbar arrays S Ghosh, R Jha, A Iyengar, R Govindaraj IEEE Transactions on Magnetics 54 (6), 1-5, 2018 | 6 | 2018 |
| Threshold-defined logic and interconnect for protection against reverse engineering JW Jang, A De, D Vontela, I Nirmala, S Ghosh, A Iyengar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 5 | 2018 |
Swaroop GhoshPennsylvania State University在 psu.edu 的电子邮件经过验证
