| Classification of focal and nonfocal EEG signals using ANFIS classifier for epilepsy detection S Deivasigamani, C Senthilpari, WH Yong International Journal of Imaging Systems and Technology 26 (4), 277-283, 2016 | 64 | 2016 |
| Retracted article: machine learning method based detection and diagnosis for epilepsy in EEG signal S Deivasigamani, C Senthilpari, WH Yong Journal of Ambient Intelligence and Humanized Computing 12 (3), 4215-4221, 2021 | 56 | 2021 |
| Design of a low-power, high performance, 8× 8 bit multiplier using a Shannon-based adder cell C Senthilpari, AK Singh, K Diwakar Microelectronics Journal 39 (5), 812-821, 2008 | 46 | 2008 |
| Low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic C Senthilpari, AK Singh, K Diwakar 2007 International Conference on Intelligent and Advanced Systems, 1374-1378, 2007 | 24 | 2007 |
| Low energy, low latency and high speed array divider circuit using a Shannon theorem based adder cell C Senthilpari, K Diwakar, AK Singh Recent patents on nanotechnology 3 (1), 61-72, 2009 | 23 | 2009 |
| Proposed low power, high speed adder-based 65-nm Square root circuit C Senthilpari, ZI Mohamad, S Kavitha Microelectronics Journal 42 (2), 445-451, 2011 | 21 | 2011 |
| Lower delay and area efficient non-restoring array divider by using Shannon based adder technique C Senthilpari, S Kavitha, J Joseph 2010 IEEE International Conference on Semiconductor Electronics (ICSE2010 …, 2010 | 19 | 2010 |
| A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture ANDZY VISHNUPRIYA SHIVAKUMAR , CHINNAIYAN SENTHILPARI, IEEE Access 9, 29366-29379, 2021 | 17 | 2021 |
| A new 6-T multiplexer based full-adder for low power and leakage current optimization GR Murthy, C Senthilpari, P Velrajkumar IEICE Electronics Express 9 (17), 1434-1441, 2012 | 15 | 2012 |
| A Low-power and High-performance Radix-4 Multiplier Design Using a Modified Pass-transistor Logic Technique C Senthilpari IETE Journal of Research 57 (2), 149-155, 2011 | 11 | 2011 |
| Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis T Bhuvaneswari, V Prasad, AK Singh, C Senthilpari International Journal of Circuit Theory and Applications 41 (8), 844-853, 2013 | 10 | 2013 |
| A new systematic GDI circuit synthesis using MUX based decomposition algorithm and binary decision diagram for low power ASIC circuit design J Ponnian, S Pari, U Ramadass, OC Pun Microelectronics Journal 108, 104963, 2021 | 8 | 2021 |
| Computer Aided Automatic Detection and Classification of EEG Signals for Screening Epilepsy Disorder. S Deivasigamani, C Senthilpari, HY Wong Journal of Information Science & Engineering 34 (3), 2018 | 7 | 2018 |
| A low power hardware implementation of S-Box for Advanced Encryption Standard K Munusamy, C Senthilpari, DCK Kho 2014 11th International Conference on Electrical Engineering/Electronics …, 2014 | 7 | 2014 |
| An efficient EPI and energy consumption of 32 bit ALU using Shannon theorem based adder approach C Senthilpari, G Ramanamurthy, P Velrajkumar WSEAS Transactions on Circuits and Systems 10 (7), 231-238, 2011 | 7 | 2011 |
| Power deduction in digital signal processing circuit using inventive CPL subtractor circuit C Senthilpari, K Diwakar, CMR Prabhu, AK Singh 2006 IEEE International Conference on Semiconductor Electronics, 820-824, 2006 | 7 | 2006 |
| Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit C Senthilpari, K Diwakar, K Munusamy, JS Francisca Engineering Science and Technology, an International Journal 20 (1), 35-40, 2017 | 6 | 2017 |
| A novel design of multiplexer based full-adder cell for power and propagation delay optimizations GR Murthy, C Senthilpari, P Velrajkumar, LIMT SZE Journal of Engineering Science and Technology 8 (6), 764-777, 2013 | 6 | 2013 |
| Highly stable Delta-Sigma Modulator for industrial applications K Diwakar, C Senthilpari, AK Singh IEICE Electronics Express 5 (15), 530-536, 2008 | 6 | 2008 |
| Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families C Senthilpari, AK Singh, A Arokiasamy 2006 International Conference on Electrical and Computer Engineering, 509-513, 2006 | 6 | 2006 |
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