| Towards high performance paged memory for GPUs T Zheng, D Nellans, A Zulfiqar, M Stephenson, SW Keckler 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 152 | 2016 |
| Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring T Zheng, J Park, M Orshansky, M Erez International Symposium on Low Power Electronics and Design (ISLPED), 229-234, 2013 | 62 | 2013 |
| SIPT: Speculatively indexed, physically tagged caches T Zheng, H Zhu, M Erez 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 28 | 2018 |
| Variation-tolerant write completion circuit for variable-energy write STT-RAM architecture J Park, T Zheng, M Erez, M Orshansky IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (4 …, 2015 | 12 | 2015 |
| Efficient fine-grained virtual memory T Zheng The University of Texas at Austin, 2018 | 2 | 2018 |
Mattan ErezThe University of Texas at Austin在 utexas.edu 的电子邮件经过验证
Mattan ErezThe University of Texas at Austin在 utexas.edu 的电子邮件经过验证
Michael OrshanskyUniversity of Texas at Austin在 utexas.edu 的电子邮件经过验证