Jiang Hu 个人学术档案 - 学术资源搜索

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	总计	2019 年至今
引用	6443	2830
h 指数	46	28
i10 指数	129	66

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Sachin SapatnekarUniversity of Minnesota在 umn.edu 的电子邮件经过验证
Chuck AlpertFellow, Cadence Design Systems在 cadence.com 的电子邮件经过验证
Yiran ChenJohn Cocke Distinguished Professor of Electrical and Computer Engineering, Duke University在 duke.edu 的电子邮件经过验证
Stephen QuayIBM在 us.ibm.com 的电子邮件经过验证
Cliff C. N. SzeGoogle在 google.com 的电子邮件经过验证
Paul V. GratzDepartment of Electrical and Computer Engineering, Texas A&M University在 tamu.edu 的电子邮件经过验证
Jeyavijayan (JV) RajendranAssociate Professor of Electrical and Computer Engineering, Texas A&M University在 tamu.edu 的电子邮件经过验证
Shiyan HuProfessor and Chair in Cyber-Physical System Security, University of Southampton在 soton.ac.uk 的电子邮件经过验证
Gi-Joon NamResearch Staff Member at IBM Research在 us.ibm.com 的电子邮件经过验证
Peng LiProfessor of Electrical & Computer Engineering, University of California, Santa Barbara在 ucsb.edu 的电子邮件经过验证
Sanchez-Sinencio EDistinguished Professor and TI J. Kilby Chair Professor of Electrical and Computer Engineering在 ece.tamu.edu 的电子邮件经过验证
Rabi MahapatraProfessor of Computer Science & Engg., Texas A&M University在 cse.tamu.edu 的电子邮件经过验证
Weiping ShiProfessor of Electrical and Computer Engineering, Texas A&M University在 ece.tamu.edu 的电子邮件经过验证
Min ZhaoSiemens在 siemens.com 的电子邮件经过验证
Anand RajaramSynopsys, University of Texas Austin, Texas A&M University在 ieee.org 的电子邮件经过验证
Farhana Sharmin SnigdhaUniversity of Minnesota在 umn.edu 的电子邮件经过验证
Sunil KhatriTexas A&M University在 tamu.edu 的电子邮件经过验证
Cheng ZhuoZhejiang University在 zju.edu.cn 的电子邮件经过验证
Xi Chengoogle在 google.com 的电子邮件经过验证
Frank LiuSchool of Data Science, Old Dominion University在 odu.edu 的电子邮件经过验证

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Jiang Hu

Professor of Electrical and Computer Engineering, Texas A&M University

在 tamu.edu 的电子邮件经过验证 - 首页

Electronic Design Automation Physical Design Architecture Resource Management Hardware Security Machine Learning and Hardwar


标题按引用次数排序按年份排序按标题排序	引用次数引用次数	年份
A practical methodology for early buffer and wire resource allocation CJ Alpert, J Hu, SS Sapatnekar, P Villarrubia Proceedings of the 38th annual Design Automation Conference, 189-194, 2001	193*	2001
Pattern sensitive placement perturbation for manufacturability S Hu, P Shah, J Hu IEEE transactions on very large scale integration (VLSI) systems 18 (6 …, 2009	190*	2009
RouteNet: Routability prediction for mixed-size designs using convolutional neural network Z Xie, YH Huang, GQ Fang, H Ren, SY Fang, Y Chen, J Hu 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018	185	2018
A timing-constrained simultaneous global routing algorithm J Hu, SS Sapatnekar IEEE Transactions on computer-aided design of integrated circuits and …, 2002	157*	2002
Joint precision optimization and high level synthesis for approximate computing C Li, W Luo, SS Sapatnekar, J Hu Proceedings of the 52nd annual design automation conference, 1-6, 2015	145	2015
Porosity aware buffered steiner tree construction CJ Alpert, G Gandham, M Hrkić, J Hu, ST Quay Proceedings of the 2003 international symposium on Physical design, 158-165, 2003	144	2003
Steiner tree optimization for buffers, blockages, and bays CJ Alpert, G Gandham, J Hu, JI Neves, ST Quay, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001	142*	2001
Reducing clock skew variability via cross links A Rajaram, J Hu, R Mahapatra Proceedings of the 41st annual Design Automation Conference, 18-23, 2004	138	2004
A survey on multi-net global routing for integrated circuits J Hu, SS Sapatnekar Integration 31 (1), 1-49, 2001	136	2001
Exploring serverless computing for neural network training L Feng, P Kudva, D Da Silva, J Hu 2018 IEEE 11th international conference on cloud computing (CLOUD), 334-341, 2018	119	2018
A new algorithm for simultaneous gate sizing and threshold voltage assignment Y Liu, J Hu Proceedings of the 2009 international symposium on Physical design, 27-34, 2009	114	2009
The cat and mouse in split manufacturing Y Wang, P Chen, J Hu, J Rajendran Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016	107	2016
Machine learning-based pre-routing timing prediction with reduced pessimism EC Barboza, N Shukla, Y Chen, J Hu Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019	100	2019
Fast algorithms for slew constrained minimum cost buffering S Hu, CJ Alpert, J Hu, S Karandikar, Z Li, W Shi, CN Sze Proceedings of the 43rd annual Design Automation Conference, 308-313, 2006	100	2006
An efficient merging scheme for prescribed skew clock routing R Chaturvedi, J Hu IEEE transactions on very large scale integration (VLSI) systems 13 (6), 750-754, 2005	99*	2005
Algorithms for gate sizing and device parameter selection for high-performance designs MM Ozdal, S Burns, J Hu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012	97*	2012
ALIGN: Open-source analog layout automation from the ground up K Kunal, M Madhusudan, AK Sharma, W Xu, SM Burns, R Harjani, J Hu, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019	96	2019
Gate sizing for cell library-based designs S Hu, M Ketkar, J Hu Proceedings of the 44th annual Design Automation Conference, 847-852, 2007	96	2007
Buffered Steiner trees for difficult instances CJ Alpert, M Hrkić, J Hu, AB Kahng, J Lillis, B Liu, ST Quay, ... Proceedings of the 2001 international symposium on Physical design, 4-9, 2001	92	2001
Standard cell characterization considering lithography induced variations K Cao, S Dobre, J Hu Proceedings of the 43rd annual Design Automation Conference, 801-804, 2006	88	2006

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