| Method and device for implementing a coinless gaming environment LE Cannon US Patent 6,746,330, 2004 | 155* | 2004 |
| Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor J Iyer, N Kosarev, S Shishlov, A Sivtsov, A Butuzov, BA Babayan, ... US Patent 9,645,819, 2017 | 44 | 2017 |
| Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor J Iyer, N Kosarev, S Shishlov, A Sivtsov, A Butuzov, BA Babayan, ... US Patent App. 13/524,240, 2013 | 44* | 2013 |
| Instruction scheduling for a multi-strand out-of-order processor BA Babayan, V Pentkovski, J Iyer, N Kosarev, SY Shishlov, AV Butuzov, ... US Patent App. 13/993,552, 2014 | 38 | 2014 |
| System Memory Power and Thermal Management in Platforms Build on Intel Centrino Duo Technology. J Iyer, CL Hall, J Shi, Y Huang Intel Technology Journal 10 (2), 2006 | 26 | 2006 |
| Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip D Ditzel, R Espasa, N Aymerich, A Baum, T Berg, J Burr, J Iyer 2021 IEEE Hot Chips 33 Symposium (HCS), 1-23, 2021 | 25 | 2021 |
| Performing partial register write operations in a processor J Iyer, JD Collins, S Winkel US Patent 10,346,170, 2019 | 17 | 2019 |
| Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order VP Jayesh Iyer, Nikolay KOSAREV, Sergey Y. Shishlov, Alexey Y. Sivtsov ... US Patent 9,632,790, 2017 | 12 | 2017 |
| Method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions in an out of order hardware software co-designed processor JD Collins, J Iyer, S Winkel, P Xekalakis, HH Chen, R Brauch US Patent App. 14/576,915, 2016 | 12 | 2016 |
| Apparatus and methods of decomposing loops to improve performance and power efficiency SP Scherbinin, J Iyer, AY Ostanevich, D Maslennikov, DG Motin, ... US Patent App. 15/392,626, 2018 | 7 | 2018 |
| Hardware apparatuses and methods to control access to a multiple bank data cache A Kluchnikov, J Iyer, SY Shishlov, BA Babayan US Patent 9,471,501, 2016 | 5 | 2016 |
| Two wire serial voltage identification protocol J Iyer, ER Stanford, W Kraipak US Patent 9,858,226, 2018 | 4 | 2018 |
| Hardware apparatuses and methods to control access to a multiple bank data cache A Kluchnikov, J Iyer, SY Shishlov, BA Babayan US Patent 10,095,623, 2018 | 3 | 2018 |
| Data negotiation using serial voltage identification communication WS Kraipak, J Iyer, ER Stanford US Patent 8,412,976, 2013 | 3 | 2013 |
| Instruction and logic for predication and implicit destination J Iyer, JD Collins, S Winkel, HH Chen US Patent 9,904,546, 2018 | 2 | 2018 |
| Instruction and logic for memory access in a clustered wide-execution machine AW Lechenko, A Efimov, SY Shishlov, J Iyer, BA Babayan US Patent App. 15/103,795, 2016 | 2 | 2016 |
| Time negotiation using serial voltage identification communication WS Kraipak, J Iyer, ER Stanford US Patent 8,417,986, 2013 | 1 | 2013 |
| Novel bus termination schemes to reduce IO power consumption on low power intel small form factor platforms R Das, J Iyer, V Suchitha, MT Tran, SA Thomas, SK Gupta, W Kraipak 2008 58th Electronic Components and Technology Conference, 521-525, 2008 | 1 | 2008 |
| Instruction and logic for predication and implicit destination J Iyer, J Collins, S Winkel, H Chen US Patent 10,884,735, 2021 | | 2021 |
| The method and apparatus for the instruction retired from office in multiple instructions string out-of-order processors for identification N Kosarev, S Shishlov, J Iyer, A Butuzov, B Babayan, A Kluchnikov CN Patent CN105,723,329 B, 2019 | | 2019 |
