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Johannes Schemmel
Johannes Schemmel
在 kip.uni-heidelberg.de 的电子邮件经过验证
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引用次数
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Neuromorphic silicon neuron circuits
G Indiveri, B Linares-Barranco, TJ Hamilton, A Schaik, ...
Frontiers in neuroscience 5, 73, 2011
15462011
A wafer-scale neuromorphic hardware system for large-scale neural modeling
J Schemmel, D Brüderle, A Grübl, M Hock, K Meier, S Millner
2010 ieee international symposium on circuits and systems (iscas), 1947-1950, 2010
8572010
Wafer-scale integration of analog neural networks
J Schemmel, J Fieres, K Meier
2008 IEEE International Joint Conference on Neural Networks (IEEE World …, 2008
3902008
Implementing synaptic plasticity in a VLSI spiking neural network model
J Schemmel, A Grubl, K Meier, E Mueller
The 2006 ieee international joint conference on neural network proceedings, 1-6, 2006
2852006
Large-scale neuromorphic spiking array processors: A quest to mimic the brain
CS Thakur, JL Molin, G Cauwenberghs, G Indiveri, K Kumar, N Qiao, ...
Frontiers in neuroscience 12, 891, 2018
2702018
Six networks on a universal neuromorphic computing substrate
T Pfeil, A Grübl, S Jeltsch, E Müller, P Müller, MA Petrovici, M Schmuker, ...
Frontiers in neuroscience 7, 39056, 2013
2192013
A self-calibrating single-chip CMOS camera with logarithmic response
M Loose, K Meier, J Schemmel
IEEE Journal of Solid-state circuits 36 (4), 586-596, 2001
1962001
Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system
S Schmitt, J Klähn, G Bellec, A Grübl, M Guettler, A Hartel, S Hartmann, ...
2017 international joint conference on neural networks (IJCNN), 2227-2234, 2017
1942017
The heidelberg spiking data sets for the systematic evaluation of spiking neural networks
B Cramer, Y Stradmann, J Schemmel, F Zenke
IEEE Transactions on Neural Networks and Learning Systems 33 (7), 2744-2757, 2020
1882020
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems
D Brüderle, MA Petrovici, B Vogginger, M Ehrlich, T Pfeil, S Millner, ...
Biological cybernetics 104, 263-296, 2011
1432011
Demonstrating hybrid learning in a flexible neuromorphic hardware system
S Friedmann, J Schemmel, A Grübl, A Hartel, M Hock, K Meier
IEEE transactions on biomedical circuits and systems 11 (1), 128-142, 2016
1402016
Demonstrating advantages of neuromorphic computation: a pilot study
T Wunderlich, AF Kungl, E Müller, A Hartel, Y Stradmann, SA Aamir, ...
Frontiers in neuroscience 13, 260, 2019
1382019
Modeling synaptic plasticity within networks of highly accelerated I&F neurons
J Schemmel, D Bruderle, K Meier, B Ostendorf
2007 IEEE international symposium on circuits and systems, 3367-3370, 2007
1302007
Is a 4-bit synaptic weight resolution enough?–constraints on enabling spike-timing dependent plasticity in neuromorphic hardware
T Pfeil, TC Potjans, S Schrader, W Potjans, J Schemmel, M Diesmann, ...
Frontiers in neuroscience 6, 22895, 2012
1202012
The BrainScaleS-2 accelerated neuromorphic system with hybrid plasticity
C Pehle, S Billaudelle, B Cramer, J Kaiser, K Schreiber, Y Stradmann, ...
Frontiers in Neuroscience 16, 795876, 2022
1172022
An accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture
SA Aamir, Y Stradmann, P Müller, C Pehle, A Hartel, A Grübl, J Schemmel, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4299-4312, 2018
1112018
Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system
D Brüderle, E Müller, AP Davison, E Muller, J Schemmel, K Meier
Frontiers in neuroinformatics 3, 362, 2009
1042009
Control of criticality and computation in spiking neuromorphic networks with plasticity
B Cramer, D Stöckel, M Kreft, M Wibral, J Schemmel, K Meier, ...
Nature communications 11 (1), 2853, 2020
1032020
Fast and energy-efficient neuromorphic deep learning with first-spike times
J Göltz, L Kriener, A Baumbach, S Billaudelle, O Breitwieser, B Cramer, ...
Nature machine intelligence 3 (9), 823-835, 2021
1012021
Realizing biological spiking network models in a configurable wafer-scale hardware system
J Fieres, J Schemmel, K Meier
2008 IEEE International Joint Conference on Neural Networks (IEEE World …, 2008
1002008
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