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Jahnavi Kasturi Rangan
Jahnavi Kasturi Rangan
Infineon Technologies, Technical University of Munich
在 tum.de 的电子邮件经过验证
标题
引用次数
引用次数
年份
Timing variability analysis of digital CMOS circuits
JK Rangan, NP Aryan, J Bargfrede, C Funke, H Graeb
Reliability by Design; 9. ITG/GMM/GI-Symposium, 1-2, 2017
52017
Design-dependent monitors based on delay sensitivity tracking
JK Rangan, NP Aryan, L Wang, J Bargfrede, C Funke, H Graeb
2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018
32018
Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis
JK Rangan, NP Aryan, J Bargfrede, L Wang, C Funke, H Graeb
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (2), 401-414, 2019
12019
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