| A wireless power and data transfer receiver achieving 75.4% effective power conversion efficiency and supporting 0.1% modulation depth for ASK demodulation D Ye, Y Wang, Y Xiang, L Lyu, H Min, CJR Shi IEEE Journal of Solid-State Circuits 55 (5), 1386-1400, 2019 | 40 | 2019 |
| A 915 MHz 175 Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance D Ye, R van der Zee, B Nauta IEEE journal of solid-state circuits 51 (12), 3114-3124, 2016 | 35 | 2016 |
| 26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience D Ye, R van der Zee, B Nauta 2016 IEEE International Solid-State Circuits Conference (ISSCC), 438-439, 2016 | 26 | 2016 |
| A 13.56 MHz wireless power and data transfer receiver achieving 75.4% effective-power-conversion efficiency with 0.1% ASK modulation depth and 9.2 mW output power Y Wang, D Ye, L Lyu, Y Xiang, H Min, CJR Shi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 142-144, 2018 | 21 | 2018 |
| A 340 nW/channel 110 dB PSRR neural recording analog front-end using replica-biasing LNA, level-shifter assisted PGA, and averaged LFP servo loop in 65 nm CMOS L Lyu, D Ye, CJR Shi IEEE Transactions on Biomedical Circuits and Systems 14 (4), 811-824, 2020 | 15 | 2020 |
| A fully-integrated 64-channel wireless neural interfacing SoC achieving 110 dB AFE PSRR and supporting 54 Mb/s symbol rate, meter-range wireless data transmission L Lyu, D Ye, R Xu, G Mu, H Zhao, Y Xiang, Y Tu, Y Zhang, CJR Shi IEEE Transactions on Circuits and Systems II: Express Briefs 67 (5), 831-835, 2020 | 10 | 2020 |
| A 340nW/channel neural recording analog front-end using replica-biasing LNAs to tolerate 200mVpp interfere from 350mV power supply L Lyu, D Ye, CJR Shi 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2019 | 8 | 2019 |
| A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving −79dBc Reference Spur and 0.496mW/GHz … R Xu, D Ye, S Li, CJR Shi 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 214-216, 2022 | 7 | 2022 |
| Analysis and design of digital injection-locked clock multipliers using bang-bang phase detectors R Xu, D Ye, CJR Shi IEEE Transactions on Circuits and Systems I: Regular Papers 69 (7), 2832-2844, 2022 | 5 | 2022 |
| 26.4 A 2.4 GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and− 83dBm Sensitivity D Ye, R Xu, CJR Shi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 414-416, 2019 | 5 | 2019 |
| A nonlinear receiver leveraging cascaded inverter-based envelope-biased LNAs for in-band interference suppression in the amplitude domain D Ye, R Xu, CJR Shi IEEE Journal of Solid-State Circuits 56 (11), 3360-3374, 2021 | 4 | 2021 |
| An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64 s Recovery Time to Electrode-DC Offset … G Mu, D Ye, L Lyu, X Zhao, CJR Shi 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 4 | 2021 |
| A 400 MHz, 8-bit, 1.75-ps resolution pipelined-two-step time-to-digital converter with dynamic time amplification Y Tu, R Xu, D Ye, L Lyu, CJR Shi 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2020 | 4 | 2020 |
| A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing D Ye, P Lu, P Andreani, R van der Zee 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 169-172, 2013 | 4 | 2013 |
| A 19-μW Blocker-Tolerant Wake-Up Receiver With− 90–dBm Energy-Enhanced Sensitivity H Ren, D Ye, B Chen, W Gong, X Jin, R Xu, L Lyu, L Xu, CJR Shi IEEE Transactions on Microwave Theory and Techniques 71 (10), 4377-4392, 2023 | 3 | 2023 |
| A two-tone wake-up receiver with an envelope-detector-first architecture using envelope biasing and active inductor load achieving 41/33dB in-band rejection to CW/AM interference D Ye, Y Tu, W Gong, R Xu, CJR Shi 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 3 | 2021 |
| A 2.0-2.9 GHz digital ring-based injection-locked clock multiplier using a self-alignment frequency tracking loop for reference spur reduction R Xu, D Ye, L Lyu, CJR Shi 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 11-14, 2020 | 2 | 2020 |
| A 2.46 GHz,− 88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with> 50dB Tolerance to In-Band Interferer D Ye, R Xu, L Lyu, CJR Shi 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2019 | 2 | 2019 |
| A 915MHz Blocker-Enhanced Wake-Up Receiver with Frequency-Hopping Two-Tone Modulation Achieving 53dB Tolerance to In-Band Interference H Ren, D Ye, B Chen, X Jin, W Gong, R Xu, CJR Shi 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 299-302, 2022 | 1 | 2022 |
| A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction G Mu, L Lyu, D Ye, CJ Richard Shi Electronics Letters 59 (7), e12774, 2023 | | 2023 |
