The CHERI capability model: Revisiting RISC in an age of risk J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ... ACM SIGARCH Computer Architecture News 42 (3), 457-468, 2014 | 396 | 2014 |
CHERI: A hybrid capability-system architecture for scalable software compartmentalization RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ... 2015 IEEE Symposium on Security and Privacy, 20-37, 2015 | 359 | 2015 |
ISA Semantics for ARMv8-a, RISC-v, and CHERI-MIPS A Armstrong, T Bauereiss, B Campbell, A Reid, KE Gray, RM Norton, ... Proceedings of the ACM on Programming Languages 3 (POPL), 1-31, 2019 | 153 | 2019 |
Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7) RNM Watson, PG Neumann, J Woodruff, M Roe, H Almatary, J Anderson, ... University of Cambridge, Computer Laboratory, 2019 | 119 | 2019 |
CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment B Davis, RNM Watson, A Richardson, PG Neumann, SW Moore, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 87 | 2019 |
Cornucopia: Temporal safety for CHERI heaps NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ... 2020 IEEE Symposium on Security and Privacy (SP), 608-625, 2020 | 74 | 2020 |
Cheri concentrate: Practical compressed capabilities J Woodruff, A Joannou, H Xia, A Fox, RM Norton, D Chisnall, B Davis, ... IEEE Transactions on Computers 68 (10), 1455-1469, 2019 | 71 | 2019 |
Fast protection-domain crossing in the CHERI capability-system architecture RNM Watson, RM Norton, J Woodruff, SW Moore, PG Neumann, ... IEEE Micro 36 (5), 38-49, 2016 | 57 | 2016 |
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process K Nienhuis, A Joannou, T Bauereiss, A Fox, M Roe, B Campbell, M Naylor, ... 2020 IEEE Symposium on Security and Privacy (SP), 1003-1020, 2020 | 54 | 2020 |
CHERI JNI: Sinking the Java security model into the C D Chisnall, B Davis, K Gudka, D Brazdil, A Joannou, J Woodruff, ... ACM SIGARCH Computer Architecture News 45 (1), 569-583, 2017 | 49 | 2017 |
Capability hardware enhanced RISC instructions: CHERI instruction-set architecture RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ... University of Cambridge, Computer Laboratory, 2015 | 34 | 2015 |
The CHERI capability model: Revisiting RISC in an age of risk. In 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ... IEEE. doi 10, 2014 | 34 | 2014 |
Bluespec Extensible RISC Implementation: BERI Hardware reference RNM Watson, J Woodruff, D Chisnall, B Davis, W Koszek, AT Markettos, ... University of Cambridge, Computer Laboratory, 2015 | 16 | 2015 |
Detailed models of instruction set architectures: From pseudocode to formal semantics A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, P Mundkur, ... Proceedings of the Automated Reasoning Workshop, 2018 | 11 | 2018 |
CHERIoT: Rethinking security for low-cost embedded systems S Amar, T Chen, D Chisnall, F Domke, N Filardo, K Liu, R Norton-Wright, ... Technical Report MSR-TR-2023-6, 2023 | 9 | 2023 |
A probability model for overflow sufficiency in small hash tables RM Norton, DP Yeager Communications of the ACM 28 (10), 1068-1075, 1985 | 8 | 1985 |
CHERIoT: Complete Memory Safety for Embedded Devices S Amar, D Chisnall, T Chen, NW Filardo, B Laurie, K Liu, R Norton, ... Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 6 | 2023 |
Hardware support for compartmentalisation RM Norton University of Cambridge, Computer Laboratory, 2016 | 6 | 2016 |
Department of computer science and technology L Wang, G Tyson, J Kangasharju, J Crowcroft, S Bayhan, J Ott, ... IEEE Transactions on Big Data, 2016 | 5 | 2016 |
The state of sail A Armstrong, T Bauereiss, B Campbell, A Reid, KE Gray, R Norton, ... SpISA 2019: Workshop on Instruction Set Architecture Specification, 2019 | 4 | 2019 |