| Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications S Askari, M Saneei International Journal of Circuit Theory and Applications 47 (2), 204-216, 2019 | 29 | 2019 |
| The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications S Salem, M Tajabadi, M Saneei AEU-International Journal of Electronics and Communications 82, 406-412, 2017 | 27 | 2017 |
| Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology S Salem, H Zandevakili, A Mahani, M Saneei IET Circuits, Devices & Systems 12 (3), 233-241, 2018 | 16 | 2018 |
| Low-latency multi-level mesh topology for NoCs M Saneei, A Afzali-Kusha, Z Navabi 2006 International Conference on Microelectronics, 36-39, 2006 | 15 | 2006 |
| Two novel low power and very high speed pulse triggered flip‐flops R Razmdideh, M Saneei International Journal of Circuit Theory and Applications 43 (12), 1925-1934, 2015 | 12 | 2015 |
| A high-resolution time-to-digital converter using a three-level resolution A Dehghani, M Saneei, A Mahani International Journal of Electronics 103 (8), 1248-1261, 2016 | 10 | 2016 |
| Serial bus encoding for low power application M Saneei, A Afzali-Kusha, Z Navabi 2006 International Symposium on System-on-Chip, 1-4, 2006 | 10 | 2006 |
| Sign bit reduction encoding for low power applications M Saneei, A Afzali-Kusha, Z Navabi Proceedings of the 42nd annual Design Automation Conference, 214-217, 2005 | 10 | 2005 |
| A novel low power and high speed double edge explicit pulse triggered level converter flip‐flop R Razmdideh, M Saneei International Journal of Circuit Theory and Applications 43 (4), 516-523, 2015 | 9 | 2015 |
| Two high-performance and low-power serial communication interfaces for on-chip interconnects M Saneei, A Afzali-Kusha, M Pedram Canadian Journal of Electrical and Computer Engineering 34 (1/2), 49-56, 2009 | 9 | 2009 |
| All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology S Salem, M Saneei AEU-International Journal of Electronics and Communications 103, 1-12, 2019 | 8 | 2019 |
| Low-power and low-latency cluster topology for local traffic NoCs M Saneei, A Afzali-Kusha, Z Navabi 2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006 | 7 | 2006 |
| An accurate and fast reliability analysis method for combinational circuits H Zandevakili, A Mahani, M Saneei COMPEL: The International Journal for Computation and Mathematics in …, 2015 | 6 | 2015 |
| Low-power pulsed hybrid flip-flop based on a C-element M Rahiminejad, M Saneei AEU-International Journal of Electronics and Communications 68 (9), 907-913, 2014 | 6 | 2014 |
| Reliability analysis of logic circuits using binary probabilistic transfer matrix H Zandevakili, A Mahani, M Saneei 2013 21st Iranian Conference on Electrical Engineering (ICEE), 1-6, 2013 | 6 | 2013 |
| Design and analysis of wide tuning range ring VCO in 65nm CMOS technology S Askari, M Saneei, S Salem Radioelectronics and Communications Systems 62 (5), 232-240, 2019 | 5 | 2019 |
| Time‐to‐digital convertor based on resolution control A Dehghani, M Saneei, A Mahani IET Circuits, Devices & Systems 9 (5), 370-376, 2015 | 5 | 2015 |
| Fault-tolerant circular routing algorithm for 3D-NoC R Alizadeh, M Saneei, M Ebrahimi 2014 International Congress on Technology, Communication and Knowledge …, 2014 | 5 | 2014 |
| Probabilistic transfer matrix with mixed binary-decimal coding for logic circuit reliability analysis H Zandevakili, A Mahani, M Saneei Journal of Circuits, Systems and Computers 22 (08), 1350064, 2013 | 5 | 2013 |
| Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology R Razmdideh, M Saneei International Journal of Circuit Theory and Applications 46 (6), 1264-1271, 2018 | 4 | 2018 |
