| Rethinking DRAM design and organization for energy-constrained multi-cores AN Udipi, N Muralimanohar, N Chatterjee, R Balasubramonian, A Davis, ... Proceedings of the 37th annual international symposium on Computer …, 2010 | 357 | 2010 |
| Usimm: the utah simulated memory module N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ... University of Utah, Tech. Rep, 1-24, 2012 | 197 | 2012 |
| LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems AN Udipi, N Muralimanohar, R Balsubramonian, A Davis, NP Jouppi ACM SIGARCH Computer Architecture News 40 (3), 285-296, 2012 | 139 | 2012 |
| Simulating DRAM controllers for future system architecture exploration A Hansson, N Agarwal, A Kolli, T Wenisch, AN Udipi 2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014 | 121 | 2014 |
| Towards scalable, energy-efficient, bus-based on-chip networks AN Udipi, N Muralimanohar, R Balasubramonian HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010 | 101 | 2010 |
| Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems AN Udipi, N Muralimanohar, R Balasubramonian, A Davis, NP Jouppi ACM SIGARCH Computer Architecture News 39 (3), 425-436, 2011 | 93 | 2011 |
| Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy N Madan, L Zhao, N Muralimanohar, A Udipi, R Balasubramonian, R Iyer, ... 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 93 | 2009 |
| Memory access methods and apparatus N Muralimanohar, AN Udipi, N Chatterjee, R Balasubramonian, AL Davis, ... US Patent 9,361,955, 2016 | 58 | 2016 |
| Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device M Shevgoor, JS Kim, N Chatterjee, R Balasubramonian, A Davis, ... Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 57 | 2013 |
| Method and system of organizing a heterogeneous memory architecture N Muralimanohar, AN Udipi, NP Jouppi US Patent App. 13/162,946, 2012 | 28 | 2012 |
| Non-uniform power access in large caches with low-swing wires AN Udipi, N Muralimanohar, R Balasubramonian 2009 International Conference on High Performance Computing (HiPC), 59-68, 2009 | 28 | 2009 |
| Memory access methods and apparatus N Muralimanohar, AN Udipi, N Chatterjee, R Balasubramonian, AL Davis, ... US Patent 9,846,550, 2017 | 25 | 2017 |
| Usimm: the utah simulated memory module a simulation infrastructure for the jwac memory scheduling championship N Chatterjee, R Balasubramonian, M Shevgoor, SH Pugsley, AN Udipi, ... Utah and Intel Corp, 2012 | 22 | 2012 |
| Variable mapping of memory accesses to regions within a memory AN Udipi, A Saidi, A Hansson, C Emmons US Patent 9,218,285, 2015 | 17 | 2015 |
| Local error detection and global error correction AN Udipi, N Muralimanohar, NP Jouppi, AL Davis, R Balasubramonian US Patent 9,600,359, 2017 | 16 | 2017 |
| Data processing apparatus, and a method of handling address translation within a data processing apparatus A Hansson, A Saidi, AN Udipi, S Diestelhorst US Patent 10,133,675, 2018 | 15 | 2018 |
| CDPU: Co-designing compression and decompression processing units for hyperscale systems S Karandikar, AN Udipi, J Choi, J Whangbo, J Zhao, S Kanev, E Lim, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 4 | 2023 |
| Designing efficient memory for future computing systems AN Udipi The University of Utah, 2012 | 4 | 2012 |
| Descriptor ring management AG Saidi, AN Udipi, ML Evans, G Blake, RG Dimond US Patent 9,697,136, 2017 | 3 | 2017 |
| Memory controller and method for controlling a memory device to process access requests issued by at least one master device A Hansson, AN Udipi, N Agarwal US Patent 11,243,898, 2022 | | 2022 |
