| A simplified polynomial-fitting algorithm for DAC and ADC BIST SK Sunter, N Nagi Proceedings International Test Conference 1997, 389-395, 1997 | 207 | 1997 |
| BIST for phase-locked loops in digital applications S Sunter, A Roy International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999 | 177 | 1999 |
| Multiple clock rate test apparatus for testing digital systems B Nadeau-Dostie, ASM Hassan, DM Burek, SK Sunter US Patent 5,349,587, 1994 | 151 | 1994 |
| Test metrics for analog parametric faults S Sunter, N Nagi Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 226-234, 1999 | 133 | 1999 |
| On-chip digital jitter measurement, from megahertz to gigahertz S Sunter, A Roy IEEE Design & Test of Computers 21 (4), 314-321, 2004 | 113 | 2004 |
| Signal multiplexing circuit N Tsiakas, SK Sunter, RG Wellard, LH Sasaki US Patent 4,646,289, 1987 | 101 | 1987 |
| Bist architecture for measurement of integrated circuit delays SK Sunter, B Nadeau-Dostie US Patent 5,923,676, 1999 | 97 | 1999 |
| Oscillation-based prebond TSV test LR Huang, SY Huang, S Sunter, KH Tsai, WT Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 78 | 2013 |
| Small delay testing for TSVs in 3-D ICs SY Huang, YH Lin, KH Tsai, WT Cheng, S Sunter, YF Chou, DM Kwai Proceedings of the 49th Annual Design Automation Conference, 1031-1036, 2012 | 73 | 2012 |
| Practical random sampling of potential defects for analog fault simulation S Sunter, K Jurga, P Dingenen, R Vanhooren 2014 International Test Conference, 1-10, 2014 | 71 | 2014 |
| High accuracy stimulus generation for A/D converter BIST A Roy, S Sunter, A Fudoli, D Appello Proceedings. International Test Conference, 1031-1039, 2002 | 68 | 2002 |
| Circuit and method for measuring jitter of high speed signals SK Sunter, APJ Roy US Patent 7,158,899, 2007 | 62 | 2007 |
| Method, system and program product for testing and/or diagnosing circuits using embedded test controller access data GA Danialy, SV Pateras, MC Howells, MJ Bell, C Mc Donald, SK Sunter US Patent 6,961,871, 2005 | 61 | 2005 |
| An automated, complete, structural test solution for SERDES S Sunter, A Roy, JF Cote 2004 International Conferce on Test, 95-104, 2004 | 61 | 2004 |
| Method and apparatus for testing digital to analog and analog to digital converters SK Sunter, N Nagi US Patent 5,659,312, 1997 | 60 | 1997 |
| Current-mirror-biased pre-charged logic circuit SK Sunter US Patent 4,797,580, 1989 | 60 | 1989 |
| Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals SK Sunter, APJ Roy US Patent 6,204,694, 2001 | 58 | 2001 |
| Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost SK Sunter, B Nadeau-Dostie Proceedings. International Test Conference, 446-455, 2002 | 54 | 2002 |
| Method and circuit for testing DC parameters of circuit input and output nodes SK Sunter US Patent 6,586,921, 2003 | 52 | 2003 |
| Using mixed-signal defect simulation to close the loop between design and test S Sunter, K Jurga, A Laidler IEEE Transactions on Circuits and Systems I: Regular Papers 63 (12), 2313-2322, 2016 | 45 | 2016 |
