关注
Jonas Svedas
Jonas Svedas
其他姓名Jonas Švedas, Svedas Jonas, Jonas {hacek over (S)}vedas
R&D Engineer
在 imec.be 的电子邮件经过验证
标题
引用次数
引用次数
年份
27.2 M0N0: A performance-regulated 0.8-to-38MHz DVFS ARM cortex-M33 SIMD MCU with 10nW sleep power
P Prabhat, B Labbe, G Knight, A Savanth, J Svedas, MJ Walker, S Jeloka, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 422-424, 2020
272020
Cache sector usage prediction
N Nikoleris, AL Sandberg, J Svedas, S Diestelhorst
US Patent 10,628,318, 2020
112020
Selective clock adjustment during read and/or write memory operations
AW Chen, R Mathur, CN Dray, Y Sarrazin, JV Poitrat, Y Jallamion-Grive, ...
US Patent 10,896,707, 2021
12021
SYSTEM, METHOD AND/DEVICE FOR MANAGING MEMORY DEVICES
SSHU Gamage, FG Redondo, J Svedas
US Patent App. 17/814,438, 2024
2024
Checkpointing
FG Redondo, SSHU Gamage, J Švedas, PAK Savanth
US Patent App. 18/316,538, 2023
2023
Checkpoint-progress status
FG Redondo, J Švedas, SSHU Gamage
US Patent App. 18/316,614, 2023
2023
Signalling power level threshold event to processing circuitry
SSHU Gamage, PAK Savanth, FG Redondo, J Švedas
US Patent App. 18/309,364, 2023
2023
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