| FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability D Lee, M Jo, K Han, K Choi Field-Programmable Technology, 2009. FPT 2009. International Conference on …, 2009 | 73 | 2009 |
| Statistical quality modeling of approximate hardware S Lee, D Lee, K Han, E Shriver, LK John, A Gerstlauer Quality Electronic Design (ISQED), 2016 17th International Symposium on, 163-168, 2016 | 40 | 2016 |
| Communication architecture synthesis of cascaded bus matrix J Yoo, D Lee, S Yoo, K Choi Proceedings of the 2007 Asia and South Pacific Design Automation Conference …, 2007 | 31 | 2007 |
| Implementation of a real-time wireless interference alignment network JW Massey, J Starr, S Lee, D Lee, A Gerstlauer, RW Heath Signals, Systems and Computers (ASILOMAR), 2012 Conference Record of the …, 2012 | 30 | 2012 |
| Dynamic power and performance back-annotation for fast and accurate functional hardware simulation D Lee, LK John, A Gerstlauer Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015 | 25 | 2015 |
| Learning-based power modeling of system-level black-box IPs D Lee, T Kim, K Han, Y Hoskote, LK John, A Gerstlauer Proceedings of the IEEE/ACM International Conference on Computer-Aided …, 2015 | 24 | 2015 |
| Hardware and software implementations of Prim’s algorithm for efficient minimum spanning tree computation A Mariano, D Lee, A Gerstlauer, D Chiou International Embedded Systems Symposium, 151-158, 2013 | 22 | 2013 |
| Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs D Lee, A Gerstlauer ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (3), 30, 2018 | 19 | 2018 |
| ODALRISC: A Small, Low power, and configurable 32-bit RISC processor I Lee, D Lee, K Choi SoC Design Conference, 2008. ISOCC'08. International 3, III-25-III-26, 2008 | 13 | 2008 |
| Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study M Jo, D Lee, K Han, K Choi Integration, the VLSI Journal 47 (2), 232-241, 2014 | 12 | 2014 |
| Memory operation inclusive instruction-set extensions and data path generation I Lee, D Lee, K Choi Application-specific Systems, Architectures and Processors, 2007. ASAP. IEEE …, 2007 | 8 | 2007 |
| Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations M Jo, D Lee, K Choi SoC Design Conference, 2008. ISOCC'08. International 3, III-29-III-30, 2008 | 5 | 2008 |
| Synthesis of optimized hardware transactors from abstract communication specifications D Lee, H Park, A Gerstlauer Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2012 | 4 | 2012 |
| Entry control in network-on-chip for memory power reduction D Lee, S Yoo, K Choi Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | 4 | 2008 |
| Learning-based system-level power modeling of hardware IPs D Lee | 1 | 2017 |
| IEEE 18th International Conference Application-specific Systems, Architectures and Processors I Lee, D Lee, K Choi | | 2007 |
