| Real time detection and tracking of human face using skin color segmentation and region properties P Kumar, M Shashidhara International Journal of Signal Processing Systems 2 (2), 102-107, 2014 | 17 | 2014 |
| Skin color segmentation for detecting human face region in image P Kumar, M Shashidhara 2014 International Conference on Communication and Signal Processing, 001-005, 2014 | 15 | 2014 |
| Investigation of self-heating effect in tree-FETs by interbridging stacked nanosheets: a reliability perspective S Srivastava, M Shashidhara, A Acharya IEEE Transactions on Device and Materials Reliability 23 (1), 58-63, 2022 | 12 | 2022 |
| Automatic tracking of traffic signs based on HSV H Rashmi, M Shashidhar, GP Kumar International Journal of Engineering Research & Technology 3 (5), 2014 | 9 | 2014 |
| Performance evaluation of high-κ dielectric ferro-spacer engineered Si/SiGe hetero-junction line TFETs: a TCAD approach S Panwar, S Srivastava, M Shashidhara, A Acharya IEEE Transactions on Dielectrics and Electrical Insulation 30 (3), 1066-1071, 2023 | 6 | 2023 |
| Investigation of field-free switching of 2-D material-based spin–orbit torque magnetic tunnel junction M Shashidhara, V Nehra, S Srivatsava, S Panwar, A Acharya IEEE Transactions on Electron Devices 70 (3), 1430-1435, 2023 | 5 | 2023 |
| Performance investigation of source/drain extension region on nanosheet FET: a digital design perspective S Srivastava, S Panwar, M Shashidhara, N Bagga, D Joshi, A Acharya 2023 Silicon Nanoelectronics Workshop (SNW), 79-80, 2023 | 3 | 2023 |
| Influences of source/drain extension region on thermal behavior of stacked nanosheet FET S Srivastava, S Panwar, M Shashidhara, L Chandra, N Mishra, A Acharya IEEE Transactions on Electron Devices, 2024 | 2 | 2024 |
| Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective S Srivastava, M Shashidhara, S Panwar, S Yadav, A Acharya Solid-State Electronics 208, 108758, 2023 | 2 | 2023 |
| Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance S Panwar, S Srivastava, M Shashidhara, D Joshi, A Acharya Solid-State Electronics 210, 108810, 2023 | 1 | 2023 |
| Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs S Panwar, S Srivastava, M Shashidhara, P Dubey, D Joshi, A Acharya 2023 Silicon Nanoelectronics Workshop (SNW), 81-82, 2023 | 1 | 2023 |
| Impact of S/D Extension Length and Sheet Stacking on Transient Behavior of Nanosheet FETs S Srivastava, S Doge, S Panwar, M Shashidhara, V Garg, S Yadav, ... 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2024 | | 2024 |
| Proposal & Investigation of Schottky Ring Engineered Reconfigurable Nanowire Transistor S Panwar, S Srivastava, M Shashidhara, N Chatterji, P Dubey, D Joshi, ... 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2024 | | 2024 |
| Impact of Unconventional Torque on the Performance of Weyl-Semimetal-Based SOT-MTJ: A Micromagnetic Study M Shashidhara, S Srivatsava, S Panwar, V Nehra, R Kamal, A Acharya IEEE Transactions on Electron Devices, 2024 | | 2024 |
| Epitaxial Layer‐Based Si/SiGe Hetero‐Junction Line Tunnel FETs: A Physical Insight A Acharya, S Panwar, S Srivastava, M Shashidhara Advanced Ultra Low‐Power Semiconductor Devices: Design and Applications, 165-186, 2023 | | 2023 |
| Spin-orbit torque magnetic tunnel junction based on 2-D materials: Impact of bias-layer on device performance M Shashidhara, S Srivastava, S Panwar, A Acharya Solid-State Electronics 208, 108757, 2023 | | 2023 |
| Configurable 8T SRAM-based Computing In-Memory Architecture for Enabling Shift Operation and Multibit Dot-Product Engines C Yeswanth, S Panwar, S Srivastava, D Joshi, M Shashidhara, A Acharya 2023 IEEE Devices for Integrated Circuit (DevIC), 330-334, 2023 | | 2023 |
| 2D Materials for Spin Orbital Torque MRAM: A Path toward Neuromorphic Computing M Shashidhara, A Acharya Emerging Low-Power Semiconductor Devices, 273-287, 2022 | | 2022 |
Abhishek AcharyaSardar Vallabhbhai National Institute of Technology Surat在 eced.svnit.ac.in 的电子邮件经过验证
