| Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies G Gao, CE Uzoh, CG Woychik, H Shen, AR Sitaram, L Wang, A Agrawal, ... US Patent 9,824,974, 2017 | 54 | 2017 |
| Thermal and electrical performance of direct bond interconnect technology for 2.5 D and 3D integrated circuits A Agrawal, S Huang, G Gao, L Wang, J DeLaCruz, L Mirkarimi 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 989-998, 2017 | 45 | 2017 |
| Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies G Gao, CE Uzoh, CG Woychik, H Shen, AR Sitaram, L Wang, A Agrawal, ... US Patent 9,548,273, 2017 | 33 | 2017 |
| Board level energy correlation and interconnect reliability modeling under drop impact A Agrawal, T Levo, J Pitarresi, B Roggeman 2009 59th Electronic Components and Technology Conference, 1694-1702, 2009 | 27 | 2009 |
| scalable approaches for 2.5d ic assembly CG Woychik, A Agrawal, R Zhang, L Mirkarimi SMTA International, 2014 | 9 | 2014 |
| Wafer-level packaging using wire bond wires in place of a redistribution layer R Katkar, TT Vu, LEE Bongsub, KM Bang, X Li, L Huynh, GZ Guevara, ... US Patent 9,502,372, 2016 | 7 | 2016 |
| Methods and structures to repair device warpage CE Uzoh, G Gao, LEE Bongsub, S McGrath, H Shen, CG Woychik, ... US Patent 9,859,234, 2018 | 5 | 2018 |
| Fan-out wafer-level packaging using metal foil lamination X Li, R Katkar, L Huynh, LW Mirkarimi, LEE Bongsub, GZ Guevara, TT Vu, ... US Patent 9,646,946, 2017 | 5 | 2017 |
| Multi-surface edge pads for vertical mount packages and methods of making package stacks R Katkar, TAO Min, JA Delacruz, H Kim, A Agrawal US Patent 10,354,945, 2019 | 4 | 2019 |
| Fan-out wafer-level packaging using metal foil lamination X Li, R Katkar, L Huynh, LW Mirkarimi, LEE Bongsub, GZ Guevara, TT Vu, ... US Patent 9,847,238, 2017 | 3 | 2017 |
| Analytical and Experimental Studies of 2.5 D Silicon Interposer Warpage: Impact of Assembly Sequences, Materials Selection and Process Parameters L Mirkarimi, R Zhang, A Agrawal, H Shaba, BS Lee, R Katkar, E Chau, ... 11th International Wafer Level Packaging Conference, San Jose, CA, 2014 | 3 | 2014 |
| Wafer level packages with mechanically decoupled fan-in and fan-out areas LEE Bongsub, TT Vu, R Katkar, LW Mirkarimi, A Agrawal, KM Bang, ... US Patent 9,543,277, 2017 | 2 | 2017 |
| Wafer-level packaging using wire bond wires in place of a redistribution layer R Katkar, TT Vu, LEE Bongsub, KM Bang, X Li, L Huynh, GZ Guevara, ... US Patent US20160322326 A1, 2016 | 2 | 2016 |
| Package-on-package interconnect for fan-out wafer level packages M Tao, A Prabhu, A Agrawal, I Mohammed, B Haba Proceedings of SMTA’s International Wafer-Level Packaging Conference, San …, 2016 | 2 | 2016 |
| Correlation between the time width of a relaxation process and the order of relaxation spectrum approximation from static measurements on glasses A Agrawal, RL Zhang Physics and chemistry of glasses 29 (4), 141-145, 1988 | 2 | 1988 |
| Substrate frame design for three-dimensional stacked electronic assemblies A Agrawal, P Ganeshbaabu US Patent App. 17/851,754, 2023 | 1 | 2023 |
| Finite Element Analysis and Measurement of Low-Profile BVATMPackage On Package (PoP) Warpage Characteristics A Agrawal, A Prabhu International Symposium on Microelectronics 2015 (1), 000157-000162, 2015 | 1 | 2015 |
| Bump pattern optimization and stress comparison study for DCA packages A Agrawal, O Fay, M Johnson 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014 | 1 | 2014 |
| Bonding of laminates with electrical interconnects JA Delacruz, B Haba, W Zohni, L Wang, A Agrawal US Patent 10,790,222, 2020 | | 2020 |
| Bonding of laminates with electrical interconnects JA Delacruz, B Haba, W Zohni, L Wang, A Agrawal US Patent 10,283,445, 2019 | | 2019 |
