Fiber: A generalized framework for auto-tuning software T Katagiri, K Kise, H Honda, T Yuba High Performance Computing: 5th International Symposium, ISHPC 2003, Tokyo …, 2003 | 91 | 2003 |
Parallel processing of matrix multiplication in a CPU and GPU heterogeneous environment S Ohshima, K Kise, T Katagiri, T Yuba High Performance Computing for Computational Science-VECPAR 2006: 7th …, 2007 | 85 | 2007 |
ABCLibScript: A directive to support specification of an auto-tuning facility for numerical software T Katagiri, K Kise, H Honda, T Yuba Parallel Computing 32 (1), 92-112, 2006 | 77 | 2006 |
A time-to-live based reservation algorithm on fully decentralized resource discovery in grid computing S Tangpongprasit, T Katagiri, K Kise, H Honda, T Yuba Parallel Computing 31 (6), 529-543, 2005 | 66 | 2005 |
High-performance hardware merge sorter S Mashimo, T Van Chu, K Kise 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 59 | 2017 |
ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility T Katagiri, K Kise, H Honda, T Yuba Parallel Computing 32 (3), 231-250, 2006 | 49 | 2006 |
Effect of auto-tuning with user's knowledge for numerical software T Katagiri, K Kise, H Honda, T Yuba Proceedings of the 1st conference on Computing frontiers, 12-25, 2004 | 43 | 2004 |
A high-performance and cost-effective hardware merge sorter without feedback datapath M Saitoh, EA Elsayed, T Van Chu, S Mashimo, K Kise 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 36 | 2018 |
Ultra-fast NoC emulation on a single FPGA T Van Chu, S Sato, K Kise 2015 25th International Conference on Field Programmable Logic and …, 2015 | 32 | 2015 |
A study of an infrastructure for research and development of many-core processors K Uehara, S Sato, T Miyoshi, K Kise 2009 International Conference on Parallel and Distributed Computing …, 2009 | 29 | 2009 |
Solving the 24-queens Problem using MPI on a PC Cluster K Kise, T Katagiri, H Honda, T Yuba Graduate School of Information Systems, The University of Electro …, 2004 | 28 | 2004 |
Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga TV Chu, S Sato, K Kise ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (4), 1-27, 2017 | 25 | 2017 |
Outline of OROCHI: A Multiple Instruction Set Executable SMT Processor H Shimada, T Shimada, T Tabata, T Kitamura, T Kojima, Y Nakashima, ... Innovative architecture for future generation high-performance processors …, 2007 | 24 | 2007 |
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs M Imai, T Van Chu, K Kise, T Yoneda 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2016 | 20 | 2016 |
A cost-effective and scalable merge sorter tree on FPGAs T Usui, T Van Chu, K Kise 2016 Fourth International Symposium on Computing and Networking (CANDAR), 47-56, 2016 | 19 | 2016 |
The simcore/alpha functional simulator K Kise, T Katagiri, H Honda, T Yuba Proceedings of the 2004 workshop on computer architecture education: held in …, 2004 | 19 | 2004 |
OROCHI: A multiple instruction set SMT processor T Nakada, Y Nakashima, H Shimada, K Kise, T Kitamura High-performance and Hardware-aware Computing (HipHaC'08), 1-8, 2008 | 18 | 2008 |
RVCoreP: An optimized RISC-V soft processor of five-stage pipelining H Miyazaki, T Kanamori, MA Islam, K Kise IEICE TRANSACTIONS on Information and Systems 103 (12), 2494-2503, 2020 | 17 | 2020 |
Towards a low-power accelerator of many FPGAs for stencil computations R Kobayashi, S Takamaeda-Yamazaki, K Kise 2012 Third International Conference on Networking and Computing, 343-349, 2012 | 15 | 2012 |
教育・研究に有用な MIPS システムシミュレータ SimMips 藤枝直輝, 渡邉伸平, 吉瀬謙二 情報処理学会論文誌 50 (11), 2665-2676, 2009 | 15 | 2009 |