| Stable SRAM cell design for the 32 nm node and beyond L Chang, DM Fried, J Hergenrother, JW Sleight, RH Dennard, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 128-129, 2005 | 860 | 2005 |
| FinFET scaling to 10 nm gate length B Yu, L Chang, S Ahmed, H Wang, S Bell, CY Yang, C Tabery, C Ho, ... Digest. International Electron Devices Meeting,, 251-254, 2002 | 848 | 2002 |
| Sub 50-nm finfet: Pmos X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ... International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 840 | 1999 |
| Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture C Hu, TJ King, V Subramanian, L Chang, X Huang, YK Choi, ... US Patent 6,413,802, 2002 | 684 | 2002 |
| Sub-50 nm P-channel FinFET X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ... IEEE Transactions on Electron Devices 48 (5), 880-886, 2001 | 618 | 2001 |
| An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches L Chang, RK Montoye, Y Nakamura, KA Batson, RJ Eickemeyer, ... IEEE Journal of Solid-State Circuits 43 (4), 956-963, 2008 | 543 | 2008 |
| A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons J Seo, B Brezzo, Y Liu, BD Parker, SK Esser, RK Montoye, B Rajendran, ... 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 454 | 2011 |
| Hybrid CMOS technology with nanowire devices and double gated planar devices S Bangsaruntip, JB Chang, L Chang, JW Sleight US Patent 8,541,774, 2013 | 412 | 2013 |
| Content addressable memory array programmed to perform logic operations L Chang, GS Ditlow, BL Ji, RK Montoye US Patent 8,059,438, 2011 | 387 | 2011 |
| Extremely scaled silicon nano-CMOS devices L Chang, Y Choi, D Ha, P Ranade, S Xiong, J Bokor, C Hu, TJ King Proceedings of the IEEE 91 (11), 1860-1873, 2003 | 372 | 2003 |
| Ultralow-voltage, minimum-energy CMOS S Hanson, B Zhai, K Bernstein, D Blaauw, A Bryant, L Chang, KK Das, ... IBM journal of research and development 50 (4.5), 469-490, 2006 | 306 | 2006 |
| Integrated circuit having gates and active regions forming a regular grating L Chang, HSP Wong, IBM Corporation, I Tuchman, M Ryan, LLP Lewis, ... US Patent 7,402,848, 2008 | 247 | 2008 |
| 1 mb 0.41 µm² 2t-2r cell nonvolatile tcam with two-bit encoding and clocked self-referenced sensing J Li, RK Montoye, M Ishii, L Chang IEEE Journal of Solid-State Circuits 49 (4), 896-907, 2013 | 246 | 2013 |
| Integrated circuit having gates and active regions forming a regular grating L Chang, HSP Wong, IBM Corporation, I Tuchman, M Ryan, LLP Lewis, ... US Patent 7,465,973, 2008 | 243 | 2008 |
| Practical strategies for power-efficient computing technologies L Chang, DJ Frank, RK Montoye, SJ Koester, BL Ji, PW Coteus, ... Proceedings of the IEEE 98 (2), 215-236, 2010 | 239 | 2010 |
| CMOS circuit performance enhancement by surface orientation optimization L Chang, M Ieong, M Yang IEEE Transactions on Electron Devices 51 (10), 1621-1627, 2004 | 225 | 2004 |
| Sub-60-nm quasi-planar FinFETs fabricated using a simplified process N Lindert, L Chang, YK Choi, EH Anderson, WC Lee, TJ King, J Bokor, ... IEEE Electron Device Letters 22 (10), 487-489, 2001 | 222 | 2001 |
| Gate length scaling and threshold voltage control of double-gate MOSFETs L Chang, S Tang, TJ King, J Bokor, C Hu International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 218 | 2000 |
| A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 L Chang, RK Montoye, BL Ji, AJ Weger, KG Stawiasz, RH Dennard 2010 Symposium on VLSI Circuits, 55-56, 2010 | 216 | 2010 |
| A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65nm CMOS L Chang, Y Nakamura, RK Montoye, J Sawada, AK Martin, K Kinoshita, ... 2007 IEEE Symposium on VLSI Circuits, 252-253, 2007 | 206 | 2007 |
