| Smart intelligent computing and applications SC Satapathy, V Bhateja, S Das Proceedings of the second international conference on SCI 1, 2018 | 60 | 2018 |
| A 1.8 V 22mW 10 bit 165 MSPS Pipelined ADC for video applications DS Shylu, DJ Moni WSEAS Transactions on Circuits and systems 13, 343-355, 2014 | 19 | 2014 |
| Design and power optimization of high-speed pipelined ADC with programmable gain amplifier for wireless receiver applications DS Shylu, DJ Moni, G Nivetha Wireless Personal Communications 90, 657-678, 2016 | 17 | 2016 |
| A novel architecture for 10-bit 40MSPS low power pipelined ADC using a simultaneous capacitor and op-amp sharing technique DSS Sam, DJ Moni, PS Paul, D Nirmal Silicon, 1-9, 2021 | 15 | 2021 |
| Design of low power dynamic comparator with reduced kickback noise using clocked PMOS technique DSSDS Shylu, DJ Moni Journal of Electrical Engineering 16 (3), 10-10, 2016 | 14 | 2016 |
| A low power dynamic comparator for a 12-bit pipelined successive approximation register (SAR) ADC DS Shylu, S Jasmine, DJ Moni 2018 4th International Conference on Devices, Circuits and Systems (ICDCS …, 2018 | 13 | 2018 |
| Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process V John, S Sam, S Radha, PS Paul, J Samuel Circuit World 46 (4), 257-269, 2020 | 11 | 2020 |
| A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique DSS Sam, PS Paul Circuit World 47 (3), 274-283, 2021 | 9 | 2021 |
| Power efficient low latency architecture for decoder: Breaking the ACS bottleneck S Radha, DS Shylu, P Nagabushanam International Journal of Circuit Theory and Applications 47 (9), 1513-1528, 2019 | 9 | 2019 |
| A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process DSS Sam, PS Paul, D Jayanthi 2021 7th International Conference on Advanced Computing and Communication …, 2021 | 8 | 2021 |
| Design of 12 Bit 100MS/s Low Power Delta Sigma ADC Using Telescopic Amplifier DS Shylu, JAM Helan, J Moni 2018 4th International Conference on Devices, Circuits and Systems (ICDCS …, 2018 | 8 | 2018 |
| Design and analysis of a two stage miller compensated op-amp suitable for ADC applications DS Shylu, DJ Moni, B Kooran IJRET: International Journal of Research in Engineering and Technology eissn …, 2014 | 8 | 2014 |
| Design of low power 4-bit Flash ADC in 90nm CMOS Process DS Shylu, S Radha, PS Paul, PS Sudeepa 2019 2nd International Conference on Signal Processing and Communication …, 2019 | 7 | 2019 |
| Design of 1-V, 12-Bit Low Power Incremental Delta Sigma ADC for CMOS Image Sensor Applications DSS Sam, S Radha, DJ Moni, PS Paul, J Jecintha International Journal of Recent Technology and Engineering (IJRTE) vol 7 …, 2019 | 6 | 2019 |
| Design of highly reusable interface for AHB verification module VT Mahendra, DSS Sam, AJ Hernisha, AJ Atchaya 2022 6th International Conference on Devices, Circuits and Systems (ICDCS …, 2022 | 5 | 2022 |
| Design of Grover’s Algorithm over 2, 3 and 4-Qubit Systems in Quantum Programming Studio D Jingle, S Sam, M Paul, J Ananth, D Selvaraj International Journal of Electronics and Telecommunications 68, 2022 | 5 | 2022 |
| Joel V John, DS Shylu, S Radha, PS Paul Design of a power efficient Kogge-Stone Adder by exploring new OR gate in …, 2020 | 5 | 2020 |
| Design of RF LNA with resistive feedback and gain peaking for multi-standard application S Radha, DS Shylu, P Nagabushanam, JS Kumari International Journal of Recent Technology and Engineering (IJRTE) 7 (4), 2018 | 5 | 2018 |
| Malware Identification in Advanced Interconnects on SOC G Sangeeth, D Jayanthi, R Krishna, P Ilanchezhian, DSS Sam 2022 International Virtual Conference on Power Engineering Computing and …, 2022 | 4 | 2022 |
| Design of Low Power Dynamic Comparator for SAR ADC AJ Herinsha, DSS Sam, AJ Atchaya 2022 6th International Conference on Devices, Circuits and Systems (ICDCS …, 2022 | 4 | 2022 |
