| 15.3 A 351TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications Q Dong, ME Sinangil, B Erbagci, D Sun, WS Khwa, HJ Liao, Y Wang, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 242-244, 2020 | 282 | 2020 |
| A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS ME Sinangil, B Erbagci, R Naous, K Akarvardar, D Sun, WS Khwa, ... IEEE Journal of Solid-State Circuits 56 (1), 188-198, 2020 | 128 | 2020 |
| A secure camouflaged threshold voltage defined logic family B Erbagci, C Erbagci, NEC Akkaya, K Mai 2016 IEEE International symposium on hardware oriented security and trust …, 2016 | 79 | 2016 |
| A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD NEC Akkaya, B Erbagci, K Mai 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 128-130, 2018 | 27 | 2018 |
| An adaptive bilateral motion estimation algorithm and its hardware architecture A Akin, M Cetin, Z Ozcan, B Erbagci, I Hamzaoglu IEEE Transactions on Consumer Electronics 58 (2), 712-720, 2012 | 20 | 2012 |
| A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm B Erbagci, NEC Akkaya, C Teegarden, K Mai 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 16 | 2015 |
| Secure chip odometers using intentional controlled aging NEC Akkaya, B Erbagci, K Mai 2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018 | 13 | 2018 |
| A DPA-resistant self-timed three-phase dual-rail pre-charge logic family NEC Akkaya, B Erbagci, R Carley, K Mai 2015 IEEE International Symposium on Hardware Oriented Security and Trust …, 2015 | 11 | 2015 |
| Combatting IC counterfeiting using secure chip odometers NEC Akkaya, B Erbagci, K Mai 2017 IEEE International Electron Devices Meeting (IEDM), 39.5. 1-39.5. 4, 2017 | 7 | 2017 |
| 15.3 A 351TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications [C]. 2020 IEEE International Solid-State Circuits Conference D Qing, ME SINANGIL, B ERBAGCI San Francisco, USA, 242-244, 2020 | 6 | 2020 |
| Deeply hardware-entangled reconfigurable logic and interconnect B Erbagci, M Bhargava, R Dondero, K Mai 2015 International Conference on ReConFigurable Computing and FPGAs …, 2015 | 6 | 2015 |
| A secure camouflaged logic family using post-manufacturing programming with a 3.6 GHz adder prototype in 65nm CMOS at 1V nominal VDD. IEEE International Solid-State Circuits … NE Akkaya, B Erbagci, K Mai DOI 10, 128-130, 2018 | 5 | 2018 |
| An inherently secure FPGA using PUF hardware-entanglement and side-channel resistant logic in 65nm bulk CMOS B Erbagci, NEC Akkaya, C Erbagci, K Mai ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), 65-68, 2019 | 4 | 2019 |
| Secure hardware-entangled field programmable gate arrays B Erbagci, NEC Akkaya, M Bhargava, R Dondero, K Mai Journal of Parallel and Distributed Computing 131, 81-96, 2019 | 3 | 2019 |
| A compact energy-efficient pseudo-static camouflaged logic family P Mohan, NEC Akkaya, B Erbagci, K Mai 2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018 | 3 | 2018 |
| A 32kb secure cache memory with dynamic replacement mapping in 65nm bulk CMOS B Erbagci, F Liu, C Cakir, NEC Akkaya, R Lee, K Mai 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015 | 3 | 2015 |
| High Temperature Processor and Memory Implementation B Erbagci MS Thesis, École Polytechnique Fédérale de Lausanne, 2011 | 2* | 2011 |
| Hardware-Entangled Inherently Secure Field Programmable Gate Arrays B Erbagci Carnegie Mellon University, 2018 | 1 | 2018 |
Ken MaiCarnegie Mellon University, Stanford University在 ece.cmu.edu 的电子邮件经过验证
