| A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking JS Kim, CS Oh, H Lee, D Lee, HR Hwang, S Hwang, B Na, J Moon, ... IEEE Journal of Solid-State Circuits 47 (1), 107-116, 2011 | 399 | 2011 |
| Defect analysis and cost-effective resilience architecture for future DRAM devices S Cha, O Seongil, H Shin, S Hwang, K Park, SJ Jang, JS Choi, GY Jin, ... 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 71 | 2017 |
| A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme YC Bae, JY Park, SJ Rhee, SB Ko, Y Jeong, KS Noh, Y Son, J Youn, ... 2012 IEEE International Solid-State Circuits Conference, 44-46, 2012 | 47 | 2012 |
| Leveraging Power-performance Relationship of Energy-efficient Modern DRAM Devices JHA Sukhan Lee, Hyunyoon Cho, Young Hoon Son, Yuhwan Ro, Nam Sung Kim IEEE Access, 2018 | 29 | 2018 |
| 23.1 a 7.5 Gb/s/pin LPDDR5 SDRAM with WCK clocking and non-target ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power KS Ha, CK Lee, D Lee, D Moon, JH Jang, HR Hwang, H Chi, J Park, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2019 | 24 | 2019 |
| 22.2 An 8.5 Gb/s/pin 12Gb-LPDDR5 SDRAM with a hybrid-bank architecture using skew-tolerant, low-power and speed-boosting techniques in a 2nd generation 10nm DRAM process HJ Chi, CK Lee, J Park, JS Heo, J Jung, D Lee, DH Kim, D Park, K Kim, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 382-384, 2020 | 21 | 2020 |
| Memory devices configured to generate pulse amplitude modulation-based DQ signals, memory controllers, and memory systems including the memory devices and the memory controllers SC Lee, SON YoungHoon, H Cho, C Youngdon, J Choi US Patent 11,574,662, 2023 | 8 | 2023 |
| A 40-Gb/s/pin low-voltage POD single-ended PAM-4 transceiver with timing calibrated reset-less slicer and bidirectional T-coil for GDDR7 application HN Rie, CS Yoon, J Byun, S Lee, G Kim, J Kim, J Park, H Cho, Y Um, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 7 | 2022 |
| SALAD: Achieving symmetric access latency with asymmetric DRAM architecture YH Son, H Cho, Y Ro, JW Lee, JH Ahn IEEE Computer Architecture Letters 16 (1), 76-79, 2016 | 7 | 2016 |
| A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process J Kim, J Park, J Byun, C Seol, CS Yoon, ES Shin, H Cho, Y Um, S Lee, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 6 | 2022 |
| A 3.2-12.8 Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics H Yoon, W Jung, J Park, J Byun, H Jin, H Cho, Y Kim, B Lim, YC Cho, ... ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 6 | 2021 |
| SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures Y Ro, H Cho, E Lee, D Jung, YH Son, JH Ahn, JW Lee 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 6 | 2017 |
| A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE H Jin, J Byun, H Cho, H Yoon, JH Park, K Kim, Y Choi, JH Choi, H Ko, ... 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 5 | 2021 |
| Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM CK Lee, J Lee, KH Kim, JS Heo, GH Cha, JH Baek, DS Moon, YJ Eom, ... 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 153-156, 2017 | 5 | 2017 |
| Understanding power-performance relationship of energy-efficient modern DRAM devices S Lee, Y Ro, YH Son, H Cho, NS Kim, JH Ahn 2017 IEEE International Symposium on Workload Characterization (IISWC), 110-111, 2017 | 5 | 2017 |
| Memory device for generating pulse amplitude modulation-based DQ signal and memory system including the same Y Um, SON YoungHoon, C Youngdon, B Jindo, H Cho, J Choi US Patent 11,587,598, 2023 | 4 | 2023 |
| Method of generating a multi-level signal using selective equalization, method of transmitting data using the same, and transmitter and memory system performing the same J Park, SON YoungHoon, H Cho, C Youngdon, J Choi US Patent App. 17/321,678, 2022 | 4 | 2022 |
| Translation device, test system including the same, and memory system including the translation device JIN Hyungmin, SON YoungHoon, H Cho, C Youngdon, J Choi US Patent 11,581,960, 2023 | 2 | 2023 |
| Memory device, controller controlling the same, memory system including the same, and operating method thereof H Cho, S Cho, SON YoungHoon, C Youngdon, J Choi US Patent 11,348,623, 2022 | 2 | 2022 |
| Transmitter circuit including selection circuit, and method of operating the selection circuit J Park, J Kim, B Jindo, S Eunseok, H Cho, C Youngdon, J Choi US Patent 11,804,838, 2023 | 1 | 2023 |
Jung Ho AhnSeoul National University在 snu.ac.kr 的电子邮件经过验证
