| A million spiking-neuron integrated circuit with a scalable communication network and interface PA Merolla, JV Arthur, R Alvarez-Icaza, AS Cassidy, J Sawada, ... Science 345 (6197), 668-673, 2014 | 4167 | 2014 |
| Neuromorphic silicon neuron circuits G Indiveri, B Linares-Barranco, TJ Hamilton, A Schaik, ... Frontiers in neuroscience 5, 73, 2011 | 1553 | 2011 |
| Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip F Akopyan, J Sawada, A Cassidy, R Alvarez-Icaza, J Arthur, P Merolla, ... IEEE transactions on computer-aided design of integrated circuits and …, 2015 | 1526 | 2015 |
| Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations BV Benjamin, P Gao, E McQuinn, S Choudhary, AR Chandrasekaran, ... Proceedings of the IEEE 102 (5), 699-716, 2014 | 1365 | 2014 |
| Convolutional networks for fast, energy-efficient neuromorphic computing MDFDSM Steven K. Esser, Paul A. Merolla, John V. Arthur, Andrew S. Cassidy ... Proceedings of the National Academy of Science 113 (41), 11441-11446, 2016 | 1207* | 2016 |
| Backpropagation for energy-efficient neuromorphic computing SK Esser, R Appuswamy, P Merolla, JV Arthur, DS Modha Advances in Neural Information Processing Systems, 1117-1125, 2015 | 1176 | 2015 |
| A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm P Merolla, J Arthur, F Akopyan, N Imam, R Manohar, DS Modha 2011 IEEE custom integrated circuits conference (CICC), 1-4, 2011 | 589 | 2011 |
| Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores AS Cassidy, P Merolla, JV Arthur, SK Esser, B Jackson, R Alvarez-Icaza, ... Neural Networks (IJCNN), The 2013 International Joint Conference on, 1-10, 2013 | 349 | 2013 |
| TrueNorth: Accelerating from zero to 64 million neurons in 10 years MV DeBole, B Taba, A Amir, F Akopyan, A Andreopoulos, WP Risk, ... Computer 52 (5), 20-29, 2019 | 215 | 2019 |
| Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores SK Esser, A Andreopoulos, R Appuswamy, P Datta, D Barch, A Amir, ... The 2013 International Joint Conference on Neural Networks (IJCNN), 1-10, 2013 | 202 | 2013 |
| Building block of a programmable neuromorphic substrate: A digital neurosynaptic core JV Arthur, PA Merolla, F Akopyan, R Alvarez, A Cassidy, S Chandra, ... the 2012 international joint conference on Neural networks (IJCNN), 1-8, 2012 | 198 | 2012 |
| Learning in silicon: Timing is everything JV Arthur, K Boahen Advances in neural information processing systems 18, 2005 | 180 | 2005 |
| Neuromorphic event-driven neural computing architecture in a scalable neural network F Akopyan, JV Arthur, R Manohar, PA Merolla, DS Modha, A Molnar, ... US Patent 8,909,576, 2014 | 168 | 2014 |
| Deep neural networks are robust to weight binarization and other non-linear distortions P Merolla, R Appuswamy, J Arthur, SK Esser, D Modha arXiv preprint arXiv:1606.01981, 2016 | 159 | 2016 |
| Expandable networks for neuromorphic chips PA Merolla, JV Arthur, BE Shi, KA Boahen IEEE Transactions on Circuits and Systems I: Regular Papers 54 (2), 301-311, 2007 | 158 | 2007 |
| Neuromorphic implementation of orientation hypercolumns TYW Choi, PA Merolla, JV Arthur, KA Boahen, BE Shi IEEE Transactions on Circuits and Systems I: Regular Papers 52 (6), 1049-1060, 2005 | 153 | 2005 |
| Silicon-neuron design: A dynamical systems approach JV Arthur, KA Boahen IEEE Transactions on Circuits and Systems I: Regular Papers 58 (5), 1034-1043, 2010 | 138 | 2010 |
| Discovering low-precision networks close to full-precision networks for efficient embedded inference JL McKinstry, SK Esser, R Appuswamy, D Bablani, JV Arthur, IB Yildiz, ... arXiv preprint arXiv:1809.04191, 2018 | 100 | 2018 |
| Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with~ 100× speedup in time-to-solution and~ 100,000× reduction in energy-to-solution AS Cassidy, R Alvarez-Icaza, F Akopyan, J Sawada, JV Arthur, ... SC'14: Proceedings of the International Conference for High Performance …, 2014 | 98 | 2014 |
| Low-power event-driven neural computing architecture in neural networks JV Arthur, PA Merolla, DS Modha US Patent 8,812,414, 2014 | 98 | 2014 |
