Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications F Minervini, O Palomar, O Unsal, E Reggiani, J Quiroga, J Marimon, ... ACM Transactions on Architecture and Code Optimization 20 (2), 1-25, 2023 | 31 | 2023 |
An academic risc-v silicon implementation based on open-source components J Abella, C Bulla, G Cabo, FJ Cazorla, A Cristal, M Doblas, R Figueras, ... 2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2020 | 23 | 2020 |
VIA: A Smart Scratchpad for Vector Units With Application to Sparse Matrix Computations J Pavon, IV Valdivieso, A Barredo, J Marimon, M Moreto, F Moll, O Unsal, ... 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 16 | 2021 |
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology G Cabo, G Candón, X Carril, M Doblas, M Domínguez, A González, ... 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 1-6, 2022 | 8 | 2022 |
A novel fpga-based high throughput accelerator for binary search trees O Melikoglu, O Ergin, B Salami, J Pavon, O Unsal, A Cristal 2019 International Conference on High Performance Computing & Simulation …, 2019 | 7 | 2019 |
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology M Doblas, G Candón, X Carril, M Domínguez, E Erra, A González, ... 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2023 | 3 | 2023 |
VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing J Pavón, IV Valdivieso, J Marimon, R Figueras, F Moll, O Unsal, M Valero, ... 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 2 | 2023 |
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms J Pavon, IV Valdivieso, C Rojas, C Hernandez, M Aslan, R Figueras, ... 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture …, 2024 | | 2024 |
Non-Conventional Vector Units for Big Data Workloads J Pavon Rivera Universitat Politècnica de Catalunya, 2017 | | 2017 |
Lagarto: First Silicon RISC-V Academic Processor Developed in Spain J Abella, G Cabo, FJ Cazorla, A Cristal, R Figueras, A González, ... | | |