| Footprints in the cache D Thiebaut, HS Stone ACM Transactions on Computer Systems (TOCS) 5 (4), 305-329, 1987 | 189 | 1987 |
| Improving disk cache hit-ratios through cache partitioning D Thiébaut, HS Stone, JL Wolf IEEE Transactions on Computers 41 (06), 665-676, 1992 | 153 | 1992 |
| On the fractal dimension of computer programs and its application to the prediction of the cache miss ratio D Thiebaut IEEE transactions on Computers 38 (7), 1012-1026, 1989 | 151 | 1989 |
| Synthetic traces for trace-driven simulation of cache memories D Thiebaut, JL Wolf, HS Stone IEEE Transactions on computers 41 (04), 388-410, 1992 | 144 | 1992 |
| A model of workloads and its use in miss-rate prediction for fully associative caches JP Singh, HS Stone, DF Thiebaut IEEE transactions on computers 41 (07), 811-825, 1992 | 87 | 1992 |
| Two economical directory schemes for large-scale cache coherent multiprocessors YC Maa, DK Pradhan, D Thiebaut ACM SIGARCH Computer Architecture News 19 (5), 10, 1991 | 70 | 1991 |
| Automatic evaluation of computer programs using Moodle's virtual programming lab (VPL) plug-in D Thiébaut Journal of Computing Sciences in Colleges 30 (6), 145-151, 2015 | 53 | 2015 |
| Not multi-, but many-core: designing integral parallel architectures for embedded computation M Maliţa, G Ştefan, D Thiébaut ACM SIGARCH Computer Architecture News 35 (5), 32-38, 2007 | 44 | 2007 |
| Modeling live and dead lines in cache memory systems A Mendelson, D Thiebaut, DK Pradhan IEEE Transactions on Computers 42 (1), 1-14, 1993 | 40 | 1993 |
| Memory engine for the inspection and manipulation of data G Stefan, D Thiebaut US Patent 6,760,821, 2004 | 34 | 2004 |
| From the fractal dimension of the intermiss gaps to the cache-miss ratio D Thiebaut IBM journal of research and development 32 (6), 796-803, 1988 | 24 | 1988 |
| A theory of cache behavior DF Thiebaut, HS Stone, JL Wolf IBM Thomas J. Watson Research Division, 1987 | 15 | 1987 |
| An analytical model for fully associative cache memories JP Singh, HS Stone, DF Thiebaut IBM TJ Watson Research Center, 1988 | 14 | 1988 |
| A hierarchical directory scheme for large-scale cache-coherent multiprocessors YC Maa, DK Pradhan, D Thiebaut Proceedings Sixth International Parallel Processing Symposium, 43-46, 1992 | 11 | 1992 |
| Associative memory device G Stefan, D Thiebaut, D Tomescu US Patent 7,069,386, 2006 | 10 | 2006 |
| DNA search and the Connex technology D Thiébaut, G Stefan, M Malita International Multi-Conference on Computing in the Global Information …, 2006 | 10 | 2006 |
| Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems. A Mendelson, D Thiébaut, DK Pradhan ICPP (1), 326-330, 1990 | 10 | 1990 |
| Pipelining the Connex array D Thiébaut, M Malita BARC07, 2007 | 9 | 2007 |
| Influence of program transients in computer cache-memories. DF Thiebaut | 6 | 1989 |
| Ziv-Lempel compression with the Connex Engine D Thiebaut, G Stefan Tech. Rep. 077, Dept. Computer Science, Smith College, Northampton, MA, 01063, 2002 | 5 | 2002 |
