| Semiconductor device K Osada, T Kawahara US Patent 7,336,526, 2008 | 411* | 2008 |
| Spin-transfer torque RAM technology: Review and prospect T Kawahara, K Ito, R Takemura, H Ohno Microelectronics Reliability 52 (4), 613-627, 2012 | 410 | 2012 |
| 2Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read T Kawahara, R Takemura, K Miura, J Hayakawa, S Ikeda, Y Lee, R Sasaki, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 308 | 2007 |
| 2 Mb SPRAM (SPin-transfer torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read T Kawahara, R Takemura, K Miura, J Hayakawa, S Ikeda, YM Lee, ... IEEE Journal of Solid-State Circuits 43 (1), 109-120, 2008 | 276 | 2008 |
| Semiconductor integrated circuit device having power reduction mechanism M Horiguchi, K Uchiyama, K Itoh, T Sakata, M Aoki, T Kawahara US Patent 5,583,457, 1996 | 247* | 1996 |
| Low-power embedded SRAM modules with expanded margins for writing M Yamaoka, N Maeda, Y Shinozaki, Y Shimazaki, K Nii, S Shimada, ... ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 211 | 2005 |
| Silicon on thin BOX: A new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control R Tsuchiya, M Horiuchi, S Kimura, M Yamaoka, T Kawahara, S Maegawa, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 192 | 2004 |
| Semiconductor memory M Yamaoka, K Osada, K Itoh, T Kawahara US Patent 7,498,637, 2009 | 175 | 2009 |
| Semiconductor integrated circuit and data processing system T Kawahara, H Sato, A Nozoe, K Yoshida, S Noda, S Kubono, H Kotani, ... US Patent 6,496,418, 2002 | 172 | 2002 |
| Review and future prospects of low-voltage RAM circuits Y Nakagome, M Horiguchi, T Kawahara, K Itoh IBM Journal of Research and Development 47 (5.6), 525-552, 2003 | 163 | 2003 |
| A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and1'/0'dual-array equalized reference scheme R Takemura, T Kawahara, K Miura, H Yamamoto, J Hayakawa, ... IEEE Journal of Solid-State Circuits 45 (4), 869-879, 2010 | 162 | 2010 |
| A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions T Ishigaki, T Kawahara, R Takemura, K Ono, K Ito, H Matsuoka, H Ohno 2010 Symposium on VLSI Technology, 47-48, 2010 | 135 | 2010 |
| Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier G Kitsukawa, K Yanagisawa, T Kawahara, R Hori, Y Nakagome, ... US Patent 4,999,519, 1991 | 134 | 1991 |
| Dynamic RAM and information processing system using the same M Nakamura, T Kawahara, K Kajigaya, K Oshima, T Takahashi, H Otori, ... US Patent 5,426,603, 1995 | 132 | 1995 |
| Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology M Yamaoka, K Osada, R Tsuchiya, M Horiuchi, S Kimura, T Kawahara 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 130 | 2004 |
| Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment M Miyazaki, H Tanaka, G Ono, T Nagano, N Ohkubo, T Kawahara, K Yano Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 129 | 2003 |
| Scalable spin-transfer torque ram technology for normally-off computing T Kawahara IEEE Design & Test of Computers 28 (1), 52-63, 2010 | 125 | 2010 |
| 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique M Yamaoka, N Maeda, Y Shinozaki, Y Shimazaki, K Nii, S Shimada, ... IEEE Journal of Solid-State Circuits 41 (3), 705-711, 2006 | 123 | 2006 |
| Current-induced magnetization switching in MgO barrier magnetic tunnel junctions with CoFeB-based synthetic ferrimagnetic free layers J Hayakawa, S Ikeda, K Miura, M Yamanouchi, YM Lee, R Sasaki, ... IEEE Transactions on Magnetics 44 (7), 1962-1967, 2008 | 119 | 2008 |
| SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect K Osada, K Yamaguchi, Y Saitoh, T Kawahara IEEE Journal of Solid-State Circuits 39 (5), 827-833, 2004 | 112 | 2004 |
