| A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS S Parikh, T Kao, Y Hidaka, J Jiang, A Toda, S Mcleod, W Walker, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 95 | 2013 |
| A single-40 Gb/s dual-20 Gb/s serializer IC with SFI-5.2 interface in 65 nm CMOS K Kanda, H Tamura, T Yamamoto, S Matsubara, M Kibune, Y Doi, ... IEEE Journal of Solid-State Circuits 44 (12), 3580-3589, 2009 | 47 | 2009 |
| A 3 Watt 39.8–44.6 Gb/s dual-mode SFI5. 2 SerDes chip set in 65 nm CMOS N Nedovic, A Kristensson, S Parikh, S Reddy, S McLeod, N Tzartzanis, ... IEEE journal of solid-state circuits 45 (10), 2016-2029, 2010 | 36 | 2010 |
| Bot networks WP Chen, L Liu, M Bahrami, S Parikh, P Junhee US Patent 10,997,258, 2021 | 23 | 2021 |
| A 4-channel 10.3 Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel Y Hidaka, T Horie, Y Koyanagi, T Miyoshi, H Osone, S Parikh, S Reddy, ... 2011 IEEE International Solid-State Circuits Conference, 346-348, 2011 | 22 | 2011 |
| A CMOS image sensor for DNA microarrays S Parikh, G Gulak, P Chow 2007 IEEE Custom Integrated Circuits Conference, 821-824, 2007 | 20 | 2007 |
| Voltage regulation circuit S Parikh US Patent App. 14/248,175, 2015 | 19 | 2015 |
| Teaching a robot to place objects in dynamic environments S Parikh US Patent 9,977,965, 2018 | 13 | 2018 |
| A 2× 22Gb/s SFI5. 2 CDR/deserializer in 65nm CMOS technology N Nedovic, S Parikh, A Kristensson, N Tzartzanis, W Walker, S Reddy, ... 2009 Symposium on VLSI Circuits, 10-11, 2009 | 11 | 2009 |
| Robotic device task learning S Parikh, WG Louie US Patent 11,014,231, 2021 | 8 | 2021 |
| Oscillator with adjustable frequency S Parikh US Patent 9,331,677, 2016 | 6 | 2016 |
| Amplifier circuit with variable tuning precision S Parikh US Patent 8,493,149, 2013 | 6 | 2013 |
| A system design methodology for reducing system integration time and facilitating modular design verification L Shannon, B Fort, S Parikh, A Patel, M Saldana, P Chow 2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006 | 6 | 2006 |
| Quarter-rate speculative decision feedback equalizer S Parikh US Patent 9,106,461, 2015 | 5 | 2015 |
| Designing an fpga soc using a standardized ip block interface L Shannon, B Fort, S Parikh, A Patel, M Saldana, P Chow Proceedings. 2005 IEEE International Conference on Field-Programmable …, 2005 | 5 | 2005 |
| Current-mode driver with built-in continuous-time linear equalization S Parikh US Patent 9,496,963, 2016 | 4 | 2016 |
| A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology JH Jiang, S Parikh, M Lionbarger, N Nedovic, T Yamamoto 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 377-380, 2014 | 4 | 2014 |
| Simulation technology for free flight system performance and survivability analysis JC Knight, SM Parikh Proceedings. The 21st Digital Avionics Systems Conference 2, 13D5-13D5, 2002 | 4 | 2002 |
| Sliced architecture for a current mode driver S Parikh, N Nedovic US Patent App. 15/250,767, 2018 | 3 | 2018 |
| Algorithmic matching of a deskew channel S Parikh, N Nedovic, WW Walker US Patent 8,432,995, 2013 | 3 | 2013 |
