Wu-Tung Cheng 个人学术档案

引用次数

	总计	2019 年至今
引用	6473	1284
h 指数	42	15
i10 指数	136	40

380

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285

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Yu HuangHiSilicon Co.在 hisilicon.com 的电子邮件经过验证
Sudhakar ReddyDepartment of ECE, University of Iowa在 engineering.uiowa.edu 的电子邮件经过验证
Dr Manish Dev SharmaProfessor of Physics and Electronics, Panjab University Chandigarh在 pu.ac.in 的电子邮件经过验证
Janusz RajskiVice President of Engineering, Siemens在 mentor.com 的电子邮件经过验证
Nilanjan MukherjeeSenior Engineering Director, Siemens Digital Industries Software在 mentor.com 的电子邮件经过验证
Shi-Yu HuangProfessor of Eletrical Engineering, National Tsing Hua University在 ee.nthu.edu.tw 的电子邮件经过验证
Liyang LaiCalypto Design Systems在 mentor.com 的电子邮件经过验证
Brady BenwareMentor, A Siemens Business在 mentor.com 的电子邮件经过验证
Janak H. PatelElectrical and Computer Engineering, University of Illinois at Urbana-Champaign在 illinois.edu 的电子邮件经过验证
Xiaoxin FanDepartment of Electrical and Computer Engineering, University of Iowa在 uiowa.edu 的电子邮件经过验证
Stephen SunterEngineering Director, Mixed-signal DFT, Mentor Graphics在 mentor.com 的电子邮件经过验证
Yu Hu (胡瑜)Institute of Computing Technology, Chinese Academy of Sciences在 ict.ac.cn 的电子邮件经过验证
Bernd BeckerProfessor of Computer Science, University of Freiburg在 informatik.uni-freiburg.de 的电子邮件经过验证
james C M LiNational Taiwan University在 cc.ee.ntu.edu.tw 的电子邮件经过验证
Mark M. TehranipoorIntel Charles E. Young Endowed Chair Professor, ECE, University of Florida在 ufl.edu 的电子邮件经过验证
Aiman El-MalehProfessor of Computer Engineering, King Fahd University of Petroleum & Minerals在 kfupm.edu.sa 的电子邮件经过验证

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Wu-Tung Cheng

chief scientist, mentor graphics

在 mentor.com 的电子邮件经过验证

design for test


标题按引用次数排序按年份排序按标题排序	引用次数引用次数	年份
PROOFS: A fast, memory-efficient sequential circuit fault simulator TM Niermann, WT Cheng, JH Patel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1992	422	1992
Gentest: an automatic test-generation system for sequential circuits WT Cheng, TJ Chakraborty Computer 22 (4), 43-49, 1989	247	1989
The BACK algorithm for sequential test generation WT Cheng Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 66 …, 1988	242	1988
Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm Y Huang, SM Reddy, WT Cheng, P Reuter, N Mukherjee, CC Tsai, ... Proceedings. International Test Conference, 74-82, 2002	213	2002
Resource allocation and test scheduling for concurrent test of core-based SOC design Y Huang, WT Cheng, CC Tsai, N Mukherjee, O Samman, Y Zaidan, ... Proceedings 10th Asian Test Symposium, 265-270, 2001	186	2001
Full-speed BIST controller for testing embedded synchronous memories WT Cheng, CJ Hill, O Kebichi US Patent 6,829,728, 2004	119*	2004
Differential fault simulation-A fast method using minimal memory WT Cheng, ML Yu Proceedings of the 26th ACM/IEEE Design Automation Conference, 424-428, 1989	113	1989
Multi-stage test response compactors J Rajski, J Tyszer, G Mrugalski, M Kassab, WT Cheng US Patent 7,818,644, 2010	97	2010
Survey of scan chain diagnosis Y Huang, R Guo, WT Cheng, JCM Li IEEE Design & Test of Computers 25 (3), 240-248, 2008	96	2008
Diagnosis for wiring interconnects WT Cheng, JL Lewandowski, E Wu Proceedings. International Test Conference 1990, 565-571, 1990	92	1990
Sequential circuit test generator (STG) benchmark results WT Cheng, S Davidson IEEE International Symposium on Circuits and Systems,, 1939-1941, 1989	88	1989
Statistical diagnosis for intermittent scan chain hold-time fault Y Huang, WT Cheng, SM Reddy, CJ Hsieh, YT Hung ITC, 319-328, 2003	85	2003
Reduced-pin-count-testing architectures for applying test patterns N Mukherjee, J Jahangiri, R Press, WT Cheng US Patent 7,487,419, 2009	82	2009
Oscillation-based prebond TSV test LR Huang, SY Huang, S Sunter, KH Tsai, WT Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013	78	2013
Full-speed field-programmable memory BIST architecture X Du, N Mukherjee, WT Cheng, SM Reddy IEEE International Conference on Test, 2005., 9 pp.-1173, 2005	77	2005
X-filter: Filtering unknowns from compacted test responses M Sharma, WT Cheng IEEE International Conference on Test, 2005., 9 pp.-1098, 2005	77	2005
Small delay testing for TSVs in 3-D ICs SY Huang, YH Lin, KH Tsai, WT Cheng, S Sunter, YF Chou, DM Kwai Proceedings of the 49th Annual Design Automation Conference, 1031-1036, 2012	73	2012
Split circuit model for test generation WT Cheng Annual ACM IEEE Design Automation Conference: Proceedings of the 25 th ACM …, 1988	71	1988
Signature based diagnosis for logic BIST WT Cheng, M Sharma, T Rinderknecht, L Lai, C Hill 2006 IEEE International Test Conference, 1-9, 2006	70	2006
Compactor independent direct diagnosis of test hardware Y Huang, WT Cheng, J Rajski US Patent 7,729,884, 2010	69	2010

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