HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores DY Hong, CC Hsu, PC Yew, JJ Wu, WC Hsu, P Liu, CM Wang, YC Chung Proceedings of the Tenth International Symposium on Code Generation and …, 2012 | 147 | 2012 |
Early experiences in application level I/O tracing on Blue Gene systems S Seelam, IH Chung, DY Hong, HF Wen, H Yu 2008 IEEE International Symposium on Parallel and Distributed Processing, 1-8, 2008 | 31 | 2008 |
Dbill: An efficient and retargetable dynamic binary instrumentation framework using llvm backend YH Lyu, DY Hong, TY Wu, JJ Wu, WC Hsu, P Liu, PC Yew Acm Sigplan Notices 49 (7), 141-152, 2014 | 24 | 2014 |
LnQ: Building high performance dynamic binary translators with existing compiler backends CC Hsu, P Liu, CM Wang, JJ Wu, DY Hong, PC Yew, WC Hsu 2011 International Conference on Parallel Processing, 226-234, 2011 | 22 | 2011 |
Simd code translation in an enhanced hqemu SY Fu, DY Hong, JJ Wu, P Liu, WC Hsu 2015 IEEE 21st International Conference on Parallel and Distributed Systems …, 2015 | 20 | 2015 |
Improving simd parallelism via dynamic binary translation DY Hong, YP Liu, SY Fu, JJ Wu, WC Hsu ACM Transactions on Embedded Computing Systems (TECS) 17 (3), 1-27, 2018 | 18 | 2018 |
Efficient and retargetable dynamic binary translation on multicores DY Hong, JJ Wu, PC Yew, WC Hsu, CC Hsu, P Liu, CM Wang, YC Chung IEEE Transactions on Parallel and Distributed Systems 25 (3), 622-632, 2013 | 17 | 2013 |
Improving dynamic binary optimization through early-exit guided code region formation CC Hsu, P Liu, JJ Wu, PC Yew, DY Hong, WC Hsu, CM Wang ACM SIGPLAN Notices 48 (7), 23-32, 2013 | 16 | 2013 |
Exploiting asymmetric SIMD register configurations in arm-to-x86 dynamic binary translation YP Liu, DY Hong, JJ Wu, SY Fu, WC Hsu 2017 26th International Conference on Parallel Architectures and Compilation …, 2017 | 15 | 2017 |
Optimal branch location for cost-effective inference on branchynet CH Chiang, P Liu, DW Wang, DY Hong, JJ Wu 2021 IEEE International Conference on Big Data (Big Data), 5071-5080, 2021 | 14 | 2021 |
Exploiting longer SIMD lanes in dynamic binary translation DY Hong, SY Fu, YP Liu, JJ Wu, WC Hsu 2016 IEEE 22nd International Conference on Parallel and Distributed Systems …, 2016 | 13 | 2016 |
Optimizing control transfer and memory virtualization in full system emulators DY Hong, CC Hsu, CY Chou, WC Hsu, P Liu, JJ Wu ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-24, 2015 | 11 | 2015 |
A dynamic binary translation system in a client/server environment CC Hsu, DY Hong, WC Hsu, P Liu, JJ Wu Journal of Systems Architecture 61 (7), 307-319, 2015 | 10 | 2015 |
Efficient and retargetable SIMD translation in a dynamic binary translator SY Fu, DY Hong, YP Liu, JJ Wu, WC Hsu Software: Practice and Experience 48 (6), 1312-1330, 2018 | 9 | 2018 |
Processor-tracing guided region formation in dynamic binary translation DY Hong, JJ Wu, YP Liu, SY Fu, WC Hsu ACM Transactions on Architecture and Code Optimization (TACO) 15 (4), 1-25, 2018 | 8 | 2018 |
MGRID: a modifiable-grid region matching approach for DDM in the HLA RTI. SH Lo, CA Chiu, FP Pai, DY Hong, YC Chung SpringSim, 2009 | 8 | 2009 |
Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator SY Fu, DY Hong, YP Liu, JJ Wu, WC Hsu Journal of Systems Architecture 98, 173-190, 2019 | 7 | 2019 |
Dynamic translation of structured loads/stores and register mapping for architectures with simd extensions SY Fu, DY Hong, YP Liu, JJ Wu, WC Hsu Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages …, 2017 | 7 | 2017 |
Exploiting SIMD asymmetry in ARM-to-x86 dynamic binary translation YP Liu, DY Hong, JJ Wu, SY Fu, WC Hsu ACM Transactions on Architecture and Code Optimization (TACO) 16 (1), 1-24, 2019 | 6 | 2019 |
A scalable HLA RTI system based on multiple-FedServ architecture DY Hong, FP Pai, SH Lo, YC Chung 2010 12th International Conference on Computer Modelling and Simulation, 527-532, 2010 | 5 | 2010 |