| Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same JM Jang, YJ Kim, SW Han, HW Song, IS Oh, HS Kim, T Hwang, HR Choi, ... US Patent 7,863,957, 2011 | 55 | 2011 |
| McDRAM v2: In-dynamic random access memory systolic array accelerator to address the large model problem in deep neural networks on the edge S Cho, H Choi, E Park, H Shin, S Yoo IEEE Access 8, 135223-135243, 2020 | 52 | 2020 |
| Memory device HR Choi, SS Chi, HS Won US Patent 10,497,421, 2019 | 32 | 2019 |
| Address counting circuit, memory device and operating method thereof JS Lee, HR Choi US Patent App. 15/623,448, 2018 | 32 | 2018 |
| Data input/output apparatus and method for semiconductor system HR Choi, YJ Kim, JM Jang US Patent 8,134,876, 2012 | 29 | 2012 |
| Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation H Choi, D Hong, J Lee, S Yoo Microprocessors and Microsystems 72, 102942, 2020 | 24 | 2020 |
| Duty cycle correction apparatus and semiconductor integrated circuit having the same JM Jang, YJ Kim, SW Han, HW Song, IS Oh, HS Kim, TJ Hwang, HR Choi, ... US Patent 7,915,939, 2011 | 21 | 2011 |
| Power noise detecting device and power noise control device using the same HS Kim, YJ Kim, SW Han, HW Song, IS Oh, T Hwang, HR Choi, JW Lee, ... US Patent 7,952,364, 2011 | 16 | 2011 |
| Integrated circuit YJ Kim, SJ Lee, HR Choi, JM Jang US Patent 8,610,475, 2013 | 14 | 2013 |
| Delay locked loop circuit and memory device having the same YJ Kim, SW Han, HW Song, IS Oh, HS Kim, T Hwang, HR Choi, JW Lee, ... US Patent 7,821,311, 2010 | 13 | 2010 |
| Data output circuit for semiconductor memory apparatus HR Choi, KW Park, YJ Kim, HW Song, IS Oh, HS Kim, T Hwang, JW Lee US Patent 7,808,841, 2010 | 11 | 2010 |
| Data output buffer circuit YJ Kim, SW Han, HW Song, IS Oh, HS Kim, TJ Hwang, HR Choi, JW Lee, ... US Patent 7,800,416, 2010 | 11 | 2010 |
| Latency control circuit, semiconductor memory device including the same, and method for controlling latency HR Choi, YJ Kim, SW Han, HW Song, IS Oh, HS Kim, T Hwang, JW Lee, ... US Patent 8,144,531, 2012 | 10 | 2012 |
| Phase mixer and delay locked loop including the same JM Jang, YJ Kim, SW Han, HW Song, IS Oh, HS Kim, T Hwang, HR Choi, ... US Patent 7,884,659, 2011 | 10 | 2011 |
| Receiver circuit for use in a semiconductor integrated circuit IS Oh, KW Park, YJ Kim, HW Song, HS Kim, T Hwang, HR Choi, JW Lee US Patent 7,868,663, 2011 | 10 | 2011 |
| Duty ratio correction circuit YJ Kim, KW Park, KH Kim, HW Song, IS Oh, HS Kim, TJ Hwang, HR Choi, ... US Patent App. 12/178,475, 2009 | 10 | 2009 |
| Semiconductor memory device and method for generating output enable signal HS Kim, YJ Kim, SW Han, HW Song, IS Oh, T Hwang, HR Choi, JW Lee, ... US Patent 8,144,530, 2012 | 9 | 2012 |
| 25.3 A 1.35 V 5.0 Gb/s/pin GDDR5M with 5.4 mW standby power and an error-adaptive duty-cycle corrector HW Lee, J Song, SA Hyun, S Baek, Y Lim, J Lee, M Park, H Choi, C Choi, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 8 | 2014 |
| Delay locked loop circuit of semiconductor device HW Song, KW Park, YJ Kim, IS Oh, HS Kim, T Hwang, HR Choi, JW Lee US Patent 7,990,785, 2011 | 8 | 2011 |
| Output driving device CK Park, YJ Kim, SW Han, HW Song, IS Oh, HS Kim, T Hwang, HR Choi, ... US Patent 7,868,667, 2011 | 8 | 2011 |
