| Formally verifying IEEE compliance of floating-point hardware J O’Leary, X Zhao, R Gerth, CJH Seger Intel Technology Journal 3 (1), 1-14, 1999 | 166 | 1999 |
| An industrially effective environment for formal hardware verification CJH Seger, RB Jones, JW O'Leary, T Melham, MD Aagaard, C Barrett, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 130 | 2005 |
| A reflective functional language for hardware design and theorem proving J Grundy, T Melham, J O'leary Journal of Functional Programming 16 (2), 157-196, 2006 | 92 | 2006 |
| Verification of all circuits in a floating-point unit using word-level model checking YA Chen, E Clarke, PH Ho, Y Hoskote, T Kam, M Khaira, J O'Leary, ... International Conference on Formal Methods in Computer-Aided Design, 19-33, 1996 | 81 | 1996 |
| Practical formal verification in microprocessor design RB Jones, JW O'Leary, CJH Seger, MD Aagaard, TF Melham IEEE design & test of computers 18 (4), 16-25, 2001 | 67 | 2001 |
| Non-restoring integer square root: A case study in design by principled optimization J O'Leary, M Leeser, J Hickey, M Aagaard International Conference on Theorem Provers in Circuit Design, 52-71, 1994 | 67 | 1994 |
| Verifying correctness of transactional memories A Cohen, JW O'Leary, A Pnueli, MR Tuttle, LD Zuck Formal Methods in Computer Aided Design (FMCAD'07), 37-44, 2007 | 59 | 2007 |
| A methodology for large-scale hardware verification MD Aagaard, RB Jones, TF Melham, JW O’Leary, CJH Seger Formal Methods in Computer-Aided Design: Third International Conference …, 2000 | 53 | 2000 |
| Codesign of communication protocols AS Wenban, JW O'Leary, GM Brown Computer 26 (12), 46-52, 1993 | 53 | 1993 |
| Protocol verification using flows: An industrial experience J O'Leary, M Talupur, MR Tuttle 2009 Formal Methods in Computer-Aided Design, 172-179, 2009 | 52 | 2009 |
| Synchronous elastic networks S Krstic, J Cortadella, M Kishinevsky, J O'Leary 2006 Formal Methods in Computer Aided Design, 19-30, 2006 | 52 | 2006 |
| Learning concise models from long execution traces NY Jeppu, T Melham, D Kroening, J O’Leary 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 30 | 2020 |
| ATLAS: automatic term-level abstraction of RTL designs BA Brady, RE Bryant, SA Seshia, JW O'Leary Eighth ACM/IEEE International Conference on Formal Methods and Models for …, 2010 | 28 | 2010 |
| Model checking transactional memory with Spin J O'Leary, B Saha, MR Tuttle 2009 29th IEEE International Conference on Distributed Computing Systems …, 2009 | 24 | 2009 |
| Verification of a subtractive radix-2 square root algorithm and implementation M Leeser, J O'Leary Proceedings of ICCD'95 International Conference on Computer Design. VLSI in …, 1995 | 24 | 1995 |
| HML: A hardware description language based on standard ML J O'Leary, M Linderman, M Leeser, M Aagaard Computer Hardware Description Languages and their applications, 327-334, 1993 | 21 | 1993 |
| Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability J Gillenwater, G Malecha, C Salama, AY Zhu, W Taha, J Grundy, ... Proceedings of the 2008 ACM SIGPLAN symposium on Partial evaluation and …, 2008 | 17 | 2008 |
| Synchronous emulation of asynchronous circuits J O'Leary, G Brown IEEE transactions on computer-aided design of integrated circuits and …, 1997 | 17 | 1997 |
| Relational STE and theorem proving for formal verification of industrial circuit designs J O'Leary, R Kaivola, T Melham 2013 Formal Methods in Computer-Aided Design, 97-104, 2013 | 16 | 2013 |
| HML: A hardware description language based on SML J O'Leary, M Linderman, M Leeser, M Aagaard Computer Hardware Description Languages and their Applications, IFIP …, 1993 | 13 | 1993 |
