| A Low-Noise Fractional- Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications Z Zong, P Chen, RB Staszewski IEEE Journal of Solid-State Circuits 54 (3), 755-767, 2018 | 64 | 2018 |
| A 31- W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS P Chen, F Zhang, Z Zong, S Hu, T Siriburanon, RB Staszewski IEEE Journal of Solid-State Circuits 54 (11), 3075-3085, 2019 | 33 | 2019 |
| A type-II phase-tracking receiver S Hu, J Du, P Chen, HM Nguyen, P Quinlan, T Siriburanon, ... IEEE Journal of Solid-State Circuits 56 (2), 427-439, 2020 | 18 | 2020 |
| A 529-μW fractional-N all-digital PLL using TDC gain auto-calibration and an inverse-class-F DCO in 65-nm CMOS P Chen, X Meng, J Yin, PI Mak, RP Martins, RB Staszewski IEEE Transactions on Circuits and Systems I: Regular Papers 69 (1), 51-63, 2021 | 16 | 2021 |
| A 2.6-to-4.1 GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving-249.4 dB FoM and-59dBc Fractional Spurs Z Gao, J He, M Fritz, J Gong, Y Shen, Z Zong, P Chen, G Spalink, B Eitel, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 380-382, 2022 | 13 | 2022 |
| A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS P Chen, F Zhang, Z Zong, H Zheng, T Siriburanon, RB Staszewski 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 93-96, 2017 | 12 | 2017 |
| Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs P Chen, XC Huang, YH Liu, M Ding, C Zhou, A Ba, K Philips, H De Groot, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 12 | 2015 |
| A 0.7-V sub-mW type-II phase-tracking Bluetooth low energy receiver in 28-nm CMOS S Hu, P Chen, P Quinlan, RB Staszewski IEEE Transactions on Circuits and Systems I: Regular Papers 68 (6), 2317-2328, 2021 | 9 | 2021 |
| A low-spur fractional-N PLL based on a time-mode arithmetic unit Z Gao, J He, M Fritz, J Gong, Y Shen, Z Zong, P Chen, G Spalink, B Eitel, ... IEEE Journal of Solid-State Circuits, 2022 | 6 | 2022 |
| An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-OrderLoop P Chen, X Huang, Y Chen, L Wu, RB Staszewski IEEE Transactions on Circuits and Systems I: Regular Papers 65 (11), 3734-3744, 2018 | 6 | 2018 |
| Mismatch analysis of DTCs with an improved BIST-TDC in 28-nm CMOS P Chen, J Yin, F Zhang, PI Mak, RP Martins, RB Staszewski IEEE Transactions on Circuits and Systems I: Regular Papers 69 (1), 196-206, 2021 | 5 | 2021 |
| A feedforward and feedback constant-slope digital-to-time converter in 28nm CMOS achieving≤ 0.12% INL/range over> 100mV supply range P Chen, F Zhang, S Hu, RB Staszewski 2021 Symposium on VLSI Circuits, 1-2, 2021 | 5 | 2021 |
| An active-under-coil RFDAC with analog linear interpolation in 28-nm CMOS F Zhang, P Chen, JS Walling, A Zhu, RB Staszewski IEEE Transactions on Circuits and Systems I: Regular Papers 68 (5), 1855-1868, 2021 | 4 | 2021 |
| Analysis and design of an 1-20 GHz track and hold circuit P Chen, S Andersson, SE Gunnarsson, H Sjöland 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 2 | 2021 |
| Fractional spur suppression in all-digital phase-locked loops P Chen, XC Huang, RB Staszewski 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2565-2568, 2015 | 2 | 2015 |
| DTC and TDC IC Design for Ultra-Low-Power ADPLL P Chen | 1 | 2014 |
| A Novel Waveform-Tracking BLE Receiver S Hu, P Chen, B Staszewski Authorea Preprints, 2023 | | 2023 |
| Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion X Meng, H Li, P Chen, J Yin, PI Mak, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | | 2023 |
| Time domain converters and ultra-low-power all-digital phase-locked-loop P Chen | | 2019 |
| Exponential extended flash time-to-digital converter P Chen, RB Staszewski 2016 Second International Conference on Event-based Control, Communication …, 2016 | | 2016 |
Robert Bogdan StaszewskiUniversity College Dublin (UCD)在 ucd.ie 的电子邮件经过验证
