| Current reusing VCO and divide-by-two frequency divider for quadrature LO generation KG Park, CY Jeong, JW Park, JW Lee, JG Jo, C Yoo IEEE Microwave and Wireless Components Letters 18 (6), 413-415, 2008 | 62 | 2008 |
| Integrated circuit and storage device including the same J Lee, H Kim, D Na, J Ihm US Patent 9,748,956, 2017 | 40 | 2017 |
| A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18- CMOS Technology YS Seo, JW Lee, HJ Kim, C Yoo, JJ Lee, CS Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 56 (1), 6-10, 2009 | 32 | 2009 |
| 7.6 1gb/s 2tb nand flash multi-chip package with frequency-boosting interface chip HJ Kim, JD Lim, JW Lee, DH Na, JH Shin, CH Kim, SW Yu, JY Shin, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 29 | 2015 |
| Buffer device supporting training operations for a plurality of memory devices, and memory module and memory system each including the buffer device JW Lee, IHM Jeong-Don, BH Jeong US Patent 10,824,575, 2020 | 14 | 2020 |
| Spread spectrum clock generation for reduced electro-magnetic interference in consumer electronics devices JW Lee, HJ Kim, C Yoo IEEE Transactions on Consumer Electronics 56 (2), 844-847, 2010 | 14 | 2010 |
| A 1.2 V 1.33 Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications HJ Kim, Y Choi, J Lee, J Byun, S Yu, D Na, J Park, K Kim, A Kavala, Y Jo, ... 2017 Symposium on VLSI Circuits, C194-C195, 2017 | 11 | 2017 |
| Integrated circuit and storage device including integrated circuit D Na, KIM ChaeHoon, H Kim, J Lee, J Ihm US Patent 9,897,650, 2018 | 9 | 2018 |
| Skew compensation technique for source-synchronous parallel DRAM interface JW Lee, HJ Kim, CS Jeong, JJ Lee, C Yoo IEEE transactions on very large scale integration (VLSI) systems 21 (11 …, 2012 | 9 | 2012 |
| A 1.8-Gb/s/Pin 16-Tb NAND flash memory multi-chip package with F-chip for high-performance and high-capacity storage D Na, J Lee, SK Lee, H Cho, J Lee, M Yang, E Song, A Kavala, T Kim, ... IEEE Journal of Solid-State Circuits 56 (4), 1129-1140, 2021 | 7 | 2021 |
| A 1.8 Gb/s/pin 16Tb NAND flash memory multi-chip package with F-chip of toggle 4.0 specification for high performance and high capacity storage systems JW Lee, D Na, A Kavala, H Cho, J Lee, M Yang, E Song, T Kim, SK Lee, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 7 | 2020 |
| Multi-chip package capable of testing internal signal lines DH Na, HJ Kim, JW Lee US Patent 10,497,670, 2019 | 7 | 2019 |
| Data alignment circuit and method of semiconductor memory apparatus CS Jeong, KT Park, CS Yoo, JW Lee, HJ Kim US Patent 8,072,822, 2011 | 7 | 2011 |
| 인덕티브 커플링 송수신 회로를 위한 신호 전달 기법 이장우， 유창식 전자공학회논문지-SD 48 (7), 17-22, 2011 | 6 | 2011 |
| Data transmitting and receiving apparatus and method, and solid state drive including the same CB Kim, J Lee, YOO Changsik, M Jeon US Patent 8,983,379, 2015 | 4 | 2015 |
| Inter-pin skew compensation scheme for 3.2-Gb/s/pin parallel interface JW Lee, H Kim, YJ Nam, CS Yoo JSTS: Journal of Semiconductor Technology and Science 10 (1), 45-48, 2010 | 4 | 2010 |
| Measurement of intersymbol interference jitter by fractional oversampling for adaptive equalization JW Lee, CH Bae, Y Kim, C Yoo IEEE Transactions on Circuits and Systems II: Express Briefs 59 (11), 716-720, 2012 | 3 | 2012 |
| Data equalizing circuit and data equalizing method CS Jeong, JJ Lee, CS Yoo, JW Lee, SJ Kang US Patent 8,520,725, 2013 | 2 | 2013 |
| Signaling scheme for inductive coupling link JW Lee, CS Yoo Journal of the Institute of Electronics Engineers of Korea SD 48 (7), 17-22, 2011 | 1 | 2011 |
| Systems and methods of correcting errors in unmatched memory devices AP Venkatesh Prasad Ramachandra, Jang Woo Lee, Srinivas Rajendra US Patent US20230386584A1, 2023 | | 2023 |
