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Shashank Banchhor
Shashank Banchhor
Analog Design Engineer, Intel
在 intel.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
A new aspect of saturation phenomenon in FinFETs and its implication on analog circuits
S Banchhor, KD Kumar, A Dwivedi, B Anand
IEEE Transactions on Electron Devices 66 (7), 2863-2868, 2019
172019
Negative-to-positive differential resistance transition in ferroelectric FET: physical insight and utilization in analog circuits
N Chauhan, N Bagga, S Banchhor, A Datta, S Dasgupta, A Bulusu
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 69 …, 2021
152021
BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective
N Chauhan, N Bagga, S Banchhor, C Garg, A Sharma, A Datta, ...
Nanotechnology 33 (8), 085203, 2021
142021
Demonstration of a novel tunnel FET with channel sandwiched by drain
N Bagga, N Chauhan, S Banchhor, D Gupta, S Dasgupta
Semiconductor Science and Technology 35 (1), 015008, 2019
142019
Investigation of trap-induced performance degradation and restriction on higher ferroelectric thickness in negative capacitance FDSOI FET
C Garg, N Chauhan, A Sharma, S Banchhor, A Doneria, S Dasgupta, ...
IEEE Transactions on Electron Devices 68 (10), 5298-5304, 2021
122021
Traps based reliability barrier on performance and revealing early ageing in negative capacitance FET
A Gupta, G Bajpai, P Singhal, N Bagga, O Prakash, S Banchhor, ...
2021 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2021
122021
Self-heating and interface traps assisted early aging revelation and reliability analysis of negative capacitance FinFET
RK Jaisawal, S Rathore, N Gandhi, PN Kondekar, S Banchhor, ...
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2023
102023
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications
J Patel, S Banchhor, S Guglani, A Dasgupta, S Roy, A Bulusu, ...
2022 35th International Conference on VLSI Design and 2022 21st …, 2022
82022
Performance study of high-k gate & spacer dielectric Dopant Segregated Schottky Barrier SOI MOSFET
SKS Banchhor, PN Kondekar
2015 2nd International Conference on Electronics and Communication Systems …, 2015
82015
Impact of random spatial fluctuation in non-uniform crystalline phases on multidomain MFIM capacitor and negative capacitance FDSOI
N Chauhan, C Garg, K Ni, AK Behera, S Yadav, S Banchhor, N Bagga, ...
2022 IEEE International Reliability Physics Symposium (IRPS), P23-1-P23-6, 2022
62022
Design and characterization of bulk driven MOS varactor based VCO at near threshold regime
LM Dani, N Mishra, SK Banchhor, S Miryala, A Doneria, B Anand
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
52018
Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET
S Rathore, RK Jaisawal, PN Kondekar, N Gandhi, S Banchhor, YS Song, ...
2023 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2023
42023
A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors
S Banchhor, N Chauhan, B Anand
Semiconductor Science and Technology 36 (3), 035005, 2021
42021
Gain stabilization methodology for FinFET amplifiers considering self-heating effect
S Banchhor, N Chauhan, A Doneria, B Anand
2021 34th International Conference on VLSI Design and 2021 20th …, 2021
32021
Influence of underlap gate length on analog/RF performance of pocket doped Schottky Barrier MOSFET
S Banchhor, S KaleP, N Kondekar
2015 2nd International Conference on Electronics and Communication Systems …, 2015
32015
Demonstration of a junctionless negative capacitance FinFET-based hydrogen gas sensor: A reliability perspective
N Gandhi, RK Jaisawal, S Rathore, PN Kondekar, S Banchhor, N Bagga
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2023
22023
Impact of underlap channel on analog/RF performance of dopant segregated Schottky barrier MOSFET on ultra thin body SOI
S Kale, S Banchhor, PN Kondekar
2016 International Conference on Emerging Trends in Engineering, Technology …, 2016
22016
Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs
S Yadav, N Chauhan, R Chawla, A Sharma, S Banchhor, R Pratap, ...
Semiconductor Science and Technology 37 (8), 085023, 2022
12022
A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET
S Yadav, N Chauhan, S Tyagi, A Sharma, S Banchhor, R Joshi, R Pratap, ...
Semiconductor Science and Technology 36 (12), 125002, 2021
12021
Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification
N Chauhan, G Bajpai, S Banchhor, N Bagga
2020 24th International Symposium on VLSI Design and Test (VDAT), 1-5, 2020
12020
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