| Estimating single-event logic cross sections in advanced technologies RC Harrington, JS Kauppila, KM Warren, YP Chen, JA Maharrey, ... IEEE Transactions on Nuclear Science 64 (8), 2115-2121, 2017 | 40 | 2017 |
| Utilizing device stacking for area efficient hardened SOI flip-flop designs JS Kauppila, TD Loveless, RC Quinn, JA Maharrey, ML Alles, ... 2014 IEEE International Reliability Physics Symposium, SE. 4.1-SE. 4.7, 2014 | 39 | 2014 |
| Angular effects on single-event mechanisms in bulk FinFET technologies P Nsengiyumva, LW Massengill, JS Kauppila, JA Maharrey, ... IEEE Transactions on Nuclear Science 65 (1), 223-230, 2017 | 34 | 2017 |
| Effect of device variants in 32 nm and 45 nm SOI on SET pulse distributions JA Maharrey, RC Quinn, TD Loveless, JS Kauppila, S Jagannathan, ... IEEE Transactions on Nuclear Science 60 (6), 4399-4404, 2013 | 33 | 2013 |
| The impact of charge collection volume and parasitic capacitance on SEUs in SOI-and bulk-FINFET D flip-flops DR Ball, ML Alles, JS Kauppila, RC Harrington, JA Maharrey, ... IEEE Transactions on Nuclear Science 65 (1), 326-330, 2017 | 29 | 2017 |
| Geometry-aware single-event enabled compact models for sub-50 nm partially depleted silicon-on-insulator technologies JS Kauppila, LW Massengill, DR Ball, ML Alles, RD Schrimpf, ... IEEE Transactions on Nuclear Science 62 (4), 1589-1598, 2015 | 28 | 2015 |
| Heavy ion SEU test data for 32nm SOI flip-flops RC Quinn, JS Kauppila, TD Loveless, JA Maharrey, JD Rowe, ... 2015 IEEE Radiation Effects Data Workshop (REDW), 1-5, 2015 | 27 | 2015 |
| Impact of single-event transient duration and electrical delay at reduced supply voltages on set mitigation techniques JA Maharrey, JS Kauppila, RC Harrington, P Nsengiyumva, DR Ball, ... IEEE Transactions on Nuclear Science 65 (1), 362-368, 2017 | 24 | 2017 |
| Effect of transistor variants on single-event transients at the 14-/16-nm bulk FinFET technology generation RC Harrington, JA Maharrey, JS Kauppila, P Nsengiyumva, DR Ball, ... IEEE Transactions on Nuclear Science 65 (8), 1807-1813, 2018 | 21 | 2018 |
| Exploiting parallelism and heterogeneity in a radiation effects test vehicle for efficient single-event characterization of nanoscale circuits JS Kauppila, JA Maharrey, RC Harrington, TD Haeffner, P Nsengiyumva, ... IEEE Transactions on Nuclear Science 65 (1), 486-494, 2017 | 19 | 2017 |
| A bias-dependent single-event-enabled compact model for bulk FinFET technologies JS Kauppila, DR Ball, JA Maharrey, RC Harrington, TD Haeffner, ... IEEE Transactions on Nuclear Science 66 (3), 635-642, 2019 | 15 | 2019 |
| Dual-interlocked logic for single-event transient mitigation JA Maharrey, JS Kauppila, RC Harrington, P Nsengiyumva, DR Ball, ... IEEE Transactions on Nuclear Science 65 (8), 1872-1878, 2017 | 14 | 2017 |
| Empirical modeling of FinFET SEU cross sections across supply voltage RC Harrington, JS Kauppila, JA Maharrey, TD Haeffner, AL Sternberg, ... IEEE Transactions on Nuclear Science 66 (7), 1427-1432, 2019 | 13 | 2019 |
| Single-event response of 22-nm fully depleted silicon-on-insulator static random access memory MC Casey, SD Stansberry, CM Seidleck, JA Maharrey, D Gamboa, ... IEEE Transactions on Nuclear Science 68 (4), 402-409, 2021 | 12 | 2021 |
| Heavy-ion induced SETs in 32nm SOI inverter chains JA Maharrey, JS Kauppila, RC Quinn, TD Loveless, EX Zhang, ... 2015 IEEE Radiation Effects Data Workshop (REDW), 1-5, 2015 | 11 | 2015 |
| Frequency trends observed in 32nm SOI flip-flops and combinational logic RC Quinn, JS Kauppila, TD Loveless, JA Maharrey, JD Rowe, ML Alles, ... IEEE Nuclear and Space Radiation Effects Conference, 2015 | 11 | 2015 |
| A first look at 22 nm FDSOI SRAM single-event test results MC Casey, S Stansberry, C Seidleck, J Maharrey, D Gamboa, J Pellish, ... Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 2018 | 4 | 2018 |
| Impact of supply voltage and particle LET on the soft error rate of logic circuits H Jiang, H Zhang, RC Harrington, JA Maharrey, JS Kauppila, ... 2018 IEEE International Reliability Physics Symposium (IRPS), 4C. 4-1-4C. 4-4, 2018 | 4 | 2018 |
| Characterization of heavy-ion induced single event transients in 32nm and 45nm silicon-on-insulator technologies JA Maharrey | 3 | 2014 |
| Dual interlocked logic circuits J Maharrey, J Kauppila, B Dennis, WT HOLMAN, LW Massengill US Patent 10,181,851, 2019 | 2 | 2019 |
Jeffrey S. KauppilaInstitute for Space and Defense Electronics, Vanderbilt University在 vanderbilt.edu 的电子邮件经过验证
