| A new class of asynchronous A/D converters based on time quantization E Allier, G Sicard, L Fesquet, M Renaudin Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003 | 286 | 2003 |
| A very high speed true random number generator with entropy assessment A Cherkaoui, V Fischer, L Fesquet, A Aubert Cryptographic Hardware and Embedded Systems-CHES 2013: 15th International …, 2013 | 142 | 2013 |
| Asynchronous FIR filters: towards a new digital processing chain F Aeschlimann, E Allier, L Fesquet, M Renaudin 10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004 | 110 | 2004 |
| Implementing asynchronous circuits on LUT based FPGAs QT Ho, JB Rigaud, L Fesquet, M Renaudin, R Rolland Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002 | 110 | 2002 |
| A self-timed ring based true random number generator A Cherkaoui, V Fischer, A Aubert, L Fesquet 2013 IEEE 19th international symposium on asynchronous circuits and systems …, 2013 | 86 | 2013 |
| Adaptive rate filtering a computationally efficient signal processing approach SM Qaisar, L Fesquet, M Renaudin Signal Processing 94, 620-630, 2014 | 76 | 2014 |
| Asynchronous level crossing analog to digital converters E Allier, G Sicard, L Fesquet, M Renaudin Measurement 37 (4), 296-309, 2005 | 69 | 2005 |
| Technology mapping for area optimized quasi delay insensitive circuits B Folco, V Brégier, L Fesquet, M Renaudin Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5 …, 2007 | 62 | 2007 |
| High-level time-accurate model for the design of self-timed ring oscillators J Hamon, L Fesquet, B Miscopein, M Renaudin 2008 14th IEEE international symposium on asynchronous circuits and systems …, 2008 | 59 | 2008 |
| FPGA architecture for multi-style asynchronous logic [full-adder example] N Huot, H Dubreuil, L Fesquet, M Renaudin Design, Automation and Test in Europe, 32-33, 2005 | 51 | 2005 |
| Programmable/stoppable oscillator based on self-timed rings E Yahya, O Elissati, H Zakaria, L Fesquet, M Renaudin 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 3-12, 2009 | 43 | 2009 |
| Spectral analysis of a signal driven sampling scheme SM Qaisar, L Fesquet, M Renaudin 2006 14th European Signal Processing Conference, 1-5, 2006 | 41 | 2006 |
| Comparison of self-timed ring and inverter ring oscillators as entropy sources in FPGAs A Cherkaoui, V Fischer, A Aubert, L Fesquet 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 38 | 2012 |
| Adaptive rate sampling and filtering based on level crossing sampling S Mian Qaisar, L Fesquet, M Renaudin EURASIP Journal on Advances in Signal Processing 2009, 1-12, 2009 | 35 | 2009 |
| Static timing analysis of asynchronous bundled-data circuits G Gimenez, A Cherkaoui, G Cogniard, L Fesquet 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems …, 2018 | 34 | 2018 |
| Computationally efficient adaptive rate sampling and filtering SM Qaisar, L Fesquet, M Renaudin 2007 15th European Signal Processing Conference, 2139-2143, 2007 | 33 | 2007 |
| PSL-based online monitoring of digital systems D Borrione, M Liu, P Ostier, L Fesquet Applications of Specification and Design Languages for SoCs: Selected papers …, 2006 | 33 | 2006 |
| IIR digital filtering of non-uniformly sampled signals via state representation L Fesquet, B Bidégaray-Fesquet Signal Processing 90 (10), 2811-2821, 2010 | 31 | 2010 |
| On-line assertion-based verification with proven correct monitors D Borrione, M Liu, K Morin-Allory, P Ostier, L Fesquet 2005 International Conference on Information and Communication Technology …, 2005 | 29 | 2005 |
| An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. SM Qaisar, L Fesquet, M Renaudin Research Letters in Signal Processing, 2008 | 28 | 2008 |
Abdelkarim CherkaouiFPGA & IC consultant (OrionIC), Co-founder and associate (HawAI.tech)在 hawai.tech 的电子邮件经过验证
