| Power reduction techniques for LDPC decoders A Darabiha, A Chan Carusone, FR Kschischang Solid-State Circuits, IEEE Journal of 43 (8), 1835-1845, 2008 | 190 | 2008 |
| A bit-serial approximate min-sum LDPC decoder and FPGA implementation A Darabiha, AC Carusone, FR Kschischang 2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006 | 136 | 2006 |
| CMOS oscillators for clock distribution and injection-locked deskew M Hossain, AC Carusone IEEE Journal of Solid-State Circuits 44 (8), 2138-2153, 2009 | 115 | 2009 |
| Analogue adaptive filters: past and present A Carusone, DA Johns IEE Proceedings-Circuits, Devices and Systems 147 (1), 82-90, 2000 | 110 | 2000 |
| Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity A Darabiha, AC Carusone, FR Kschischang 2005 IEEE International Symposium on Circuits and Systems, 5194-5197, 2005 | 107 | 2005 |
| A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees S Shahramian, SP Voinigescu, AC Carusone IEEE journal of solid-state circuits 44 (6), 1709-1720, 2009 | 102 | 2009 |
| Block-interlaced LDPC decoders with reduced interconnect complexity A Darabiha, AC Carusone, FR Kschischang IEEE Transactions on Circuits and Systems II: Express Briefs 55 (1), 74-78, 2008 | 99 | 2008 |
| A 30-GS/sec track and hold amplifier in 0.13-μm CMOS technology S Shahramian, SP Voinigescu, AC Carusone IEEE Custom Integrated Circuits Conference 2006, 493-496, 2006 | 89 | 2006 |
| A Digital Phase-Locked Loop with Calibrated Coarse and Stochastic Fine TDC A Samarah, AC Carusone Custom Integrated Circuits Conference, 2012 | 87 | 2012 |
| A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET L Wang, Y Fu, MA LaCroix, E Chong, AC Carusone Solid-State Circuits Conference-(ISSCC), 2018 IEEE International, 110-112, 2018 | 80 | 2018 |
| All-digital calibration of timing mismatch error in time-interleaved analog-to-digital converters S Chen, L Wang, H Zhang, R Murugesu, D Dunwell, AC Carusone IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017 | 72 | 2017 |
| A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS A Darabiha, AC Carusone, FR Kschischang 2007 IEEE Custom Integrated Circuits Conference, 459-462, 2007 | 71 | 2007 |
| A Nano-Watt MOS-Only Voltage Reference With High-Slope PTAT Voltage Generators H Zhang, X Liu, J Zhang, H Zhang, J Li, R Zhang, S Chen, AC Carusone IEEE Transactions on Circuits and Systems II: Express Briefs 65 (1), 1-5, 2018 | 70 | 2018 |
| Modeling Oscillator Injection Locking Using the Phase Domain Response D Dunwell, AC Carusone IEEE Transactions on Circuits and Systems I, 2823-2833, 2013 | 68 | 2013 |
| Design of a dual W-and D-band PLL S Shahramian, A Hart, A Tomkins, AC Carusone, P Garcia, P Chevalier, ... IEEE Journal of Solid-State Circuits 46 (5), 1011-1022, 2011 | 67 | 2011 |
| A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE A Sharif-Bakhtiar, AC Carusone IEEE Journal of Solid-State Circuits 51 (11), 2679-2689, 2016 | 66 | 2016 |
| Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-SiGe BiCMOS Technology S Shahramian, AC Carusone, SP Voinigescu Solid-State Circuits, IEEE Journal of 41 (10), 2233-2240, 2006 | 62 | 2006 |
| A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-SiGe BiCMOS Technology A Garg, AC Carusone, SP Voinigescu Solid-State Circuits, IEEE Journal of 41 (10), 2224-2232, 2006 | 58 | 2006 |
| A 1-tap 40-Gbps look-ahead decision feedback equalizer in 0.18 μm SiGe BiCMOS technology A Garg, AC Carusone, SP Voinigescu Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC'05. IEEE, 4 pp., 2005 | 58* | 2005 |
| A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization TSC Kao, FA Musa, AC Carusone IEEE Transactions on Circuits and Systems I: Regular Papers 57 (11), 2844-2857, 2010 | 56 | 2010 |
Dustin DunwellPh.D. Candidate, University of Toronto在 utoronto.ca 的电子邮件经过验证
