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Shunsuke Nemoto
Shunsuke Nemoto
Kanagawa Institute of Industrial Science and Technology
在 kistec.jp 的电子邮件经过验证 - 首页
标题
引用次数
引用次数
年份
Method of manufacturing semiconductor device and semiconductor device manufacturing apparatus
M Aoyagi, TT Bui, M Suzuki, N Watanabe, F Kato, LN Ma, S Nemoto
US Patent 9,627,347, 2017
172017
Sub-micron-accuracy gold-to-gold interconnection flip-chip bonding approach for electronics–optics heterogeneous integration
BT Tung, M Suzuki, F Kato, S Nemoto, N Watanabe, M Aoyagi
Japanese Journal of Applied Physics 52 (4S), 04CB08, 2013
152013
Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking
M Aoyagi, F Imura, S Nemoto, N Watanabe, F Kato, K Kikuchi, ...
2012 2nd IEEE CPMT Symposium Japan, 1-4, 2012
122012
15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications
BT Tung, F Kato, N Watanabe, S Nemoto, K Kikuchi, M Aoyagi
Japanese Journal of Applied Physics 53 (4S), 04EB04, 2014
112014
Development of micro bump joints fabrication process using cone shape Au bumps for 3D LSI chip stacking
F Imura, N Watanabe, S Nemoto, W Feng, K Kikuchi, H Nakagawa, ...
2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 1915-1920, 2014
102014
Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications
TT Bui, M Suzuki, F Kato, N Watanabe, S Nemoto, K Kikuchi, M Aoyagi
2013 IEEE 63rd Electronic Components and Technology Conference, 425-430, 2013
92013
ナノ粒子堆積技術による Au 錐形バンプの作製
居村史人, 劉小軍, 根本俊介, 加藤史樹, 菊地克弥, 鈴木基史, 仲川博, ...
エレクトロニクス実装学術講演大会講演論文集 第 25 回エレクトロニクス実装学術講演大会 …, 2011
92011
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking
M Aoyagi, N Watanabe, M Suzuki, K Kikuchi, S Nemoto, N Arima, ...
2013 IEEE International 3D Systems Integration Conference (3DIC), 1-5, 2013
52013
Development of testing technology for wide bus chip-to-chip interconnection in 3D LSI chip stacking system
M Aoyagi, F Imura, S Melamed, S Nemoto, N Watanabe, K Kikuchi, ...
Workshop Digest of 4th IEEE International Workshop on Testing 3D Stacked ICs, 2013
52013
Investigation of Mechanism of Corrosion Resistance of Pd Coated Cu Wire Joint by Pseudo Process
Shunsuke Nemoto, Takehiko Maeda, Masahiro Miyajima, Yasuhiko Akaike ...
2019 International Conference on Electronics Packaging (ICEP), 56-60, 2019
42019
Developing a leading practical application for 3D IC chip stacking technology—How to progress from fundamental technology to application technology—
M Aoyagi, F Imura, F Kato, K Kikuchi, N Watanabe, M Suzuki, ...
Synthesiology English edition 9 (1), 1-15, 2016
42016
LSI チップ上への Au 錐形バンプの作製とフリップチップ接続
居村史人, 根本俊介, 渡辺直也, 加藤史樹, 菊地克弥, 仲川博, 青柳昌宏, ...
エレクトロニクス実装学術講演大会講演論文集 第 26 回エレクトロニクス実装学術講演大会 …, 2012
42012
Fine Cone-shaped Bumps for Three-dimensional LSI Package--An Optimization of Thermocompression Bonding Process.
S Nemoto, YY Lim, H Nakagawa, K Kikuchi, M Aoyagi
Sensors & Materials 30, 2018
32018
ナノパーティクルデポジション法を用いた微細円錐金バンプ接合配列の作製と評価
根本俊介, 居村史人, 加藤史樹, 渡辺直也, 仲川博, 青柳昌宏, 菊地克弥
エレクトロニクス実装学術講演大会講演論文集 第 27 回エレクトロニクス実装学術講演大会 …, 2013
32013
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits
S Melamed, N Watanabe, S Nemoto, H Shimamoto, K Kikuchi, M Aoyagi
Microelectronics Reliability 67, 2-8, 2016
22016
3 次元積層実装に向けたフリップチップ接続用の微細円錐金バンプの作製とバンプ圧縮評価
根本俊介, BUIT Tung, 馮ウェイ, 菊地克弥, 加藤史樹, 仲川博, 青柳昌宏
電子情報通信学会論文誌 C 99 (6), 314-320, 2016
22016
3 次元 IC 積層実装技術の実用化への取り組み―基盤技術から実用技術へどのようにしてステップアップするのか?―
青柳昌宏, 居村史人, 加藤史樹, 菊地克弥, 渡辺直也, 鈴木基史, 仲川博, ...
Synthesiology 9 (1), 1-14, 2016
22016
Investigation into the thermal effects of thinning stacked dies in three-dimensional integrated circuits
S Melamed, N Watanabe, S Nemoto, K Kikuchi, M Aoyagi
2015 21st International Workshop on Thermal Investigations of ICs and …, 2015
22015
-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications
TT Bui, F Kato, N Watanabe
Japanese Journal of Applied Physics 53, 04EB04, 2014
22014
Erratum:“Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics–Optics Heterogeneous Integration”
TT Bui, M Suzuki, F Kato, S Nemoto, N Watanabe, M Aoyagi
Japanese Journal of Applied Physics 52 (6R), 069202, 2013
22013
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