Fpga-accelerated simulation technologies (fast): Fast, full-system, cycle-accurate simulators D Chiou, D Sunwoo, J Kim, NA Patil, W Reinhart, DE Johnson, J Keefe, ... 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 254 | 2007 |
The FAST methodology for high-speed SoC/computer simulation D Chiou, D Sunwoo, J Kim, N Patil, WH Reinhart, DE Johnson, Z Xu 2007 IEEE/ACM International Conference on Computer-Aided Design, 295-302, 2007 | 61 | 2007 |
PrEsto: An FPGA-accelerated power estimation methodology for complex systems D Sunwoo, GY Wu, NA Patil, D Chiou 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 46 | 2010 |
Fpga-based fast, cycle-accurate, full-system simulators D Chiou, H Sunjeliwala, D Sunwoo, J Xu, N Patil Proceedings of the second Workshop on Architecture Research using FPGA …, 2006 | 41 | 2006 |
Chained split execution of fused compound arithmetic operations T Elmer, NA Patil US Patent 11,061,672, 2021 | 39 | 2021 |
Accurate functional-first multicore simulators D Chiou, H Angepat, N Patil, D Sunwoo IEEE Computer Architecture Letters 8 (2), 64-67, 2009 | 36 | 2009 |
Parallelizing computer system simulators D Chiou, D Sunwoo, H Angepat, J Kim, NA Patil, W Reinhart, DE Johnson 2008 IEEE International Symposium on Parallel and Distributed Processing, 1-5, 2008 | 15 | 2008 |
System and method of accelerating arbitration by approximating relative ages NA Patil US Patent 10,838,883, 2020 | 5 | 2020 |
Enforcing architectural contracts in high-level synthesis N Patil, A Bansal, D Chiou Proceedings of the 48th Design Automation Conference, 824-829, 2011 | 3 | 2011 |
Lessons from Implementing a FAST Prototype D Chiou, D Sunwoo, N Patil, J Kim, B Reinhart, H Angepat, DE Johnson 3rd Workshop on Architectural Research Prototyping (WARP’08), Beijing, China, 2008 | 2 | 2008 |
Implementing microprocessors from simplified descriptions NA Patil, D Chiou 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 787-793, 2013 | | 2013 |
Detecting and correcting out-of-order state accesses using data D Chiou, H Angepat, N Patil US Patent App. 12/749,595, 2010 | | 2010 |