| A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-Integrated Jitter at 4.5-mW Power D Tasca, M Zanuso, G Marzin, S Levantino, C Samori, AL Lacaita IEEE Journal of Solid-State Circuits 46 (12), 2745-2758, 2011 | 293 | 2011 |
| Noise analysis and minimization in bang-bang digital PLLs M Zanuso, D Tasca, S Levantino, A Donadel, C Samori, AL Lacaita IEEE Transactions on Circuits and Systems II: Express Briefs 56 (11), 835-839, 2009 | 123 | 2009 |
| A wideband 3.6 GHz digital ΔΣ fractional-N PLL with phase interpolation divider and digital spur cancellation M Zanuso, S Levantino, C Samori, AL Lacaita IEEE Journal of Solid-State Circuits 46 (3), 627-638, 2011 | 108 | 2011 |
| Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL M Zanuso, P Madoglio, S Levantino, C Samori, AL Lacaita IEEE Transactions on Circuits and Systems I: Regular Papers 57 (3), 548-555, 2009 | 71 | 2009 |
| A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration S Levantino, G Marzin, C Samori, AL Lacaita IEEE Journal of Solid-State Circuits 48 (10), 2419-2429, 2013 | 62 | 2013 |
| Quantization effects in all-digital phase-locked loops P Madoglio, M Zanuso, S Levantino, C Samori, AL Lacaita IEEE Transactions on Circuits and Systems II: Express Briefs 54 (12), 1120-1124, 2007 | 54 | 2007 |
| Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6 GHz band S Levantino, M Zanuso, C Samori, A Lacaita 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 50-51, 2010 | 52 | 2010 |
| A 3MHz-BW 3.6 GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation M Zanuso, S Levantino, C Samori, A Lacaita 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 476-477, 2010 | 40 | 2010 |
| Time-to-digital converter with 3-ps resolution and digital linearization algorithm M Zanuso, S Levantino, A Puggelli, C Samori, AL Lacaita 2010 Proceedings of ESSCIRC, 262-265, 2010 | 36 | 2010 |
| Electronic device for generating a fractional frequency S Levantino, C Samori, M Zanuso US Patent 8,571,161, 2013 | 22 | 2013 |
| Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs C Samori, M Zanuso, S Levantino, AL Lacaita 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 418-421, 2011 | 20 | 2011 |
| Low-power divider retiming in a 3–4 GHz fractional-N PLL D Tasca, M Zanuso, S Levantino, C Samori, AL Lacaita IEEE Transactions on Circuits and Systems II: Express Briefs 58 (4), 200-204, 2011 | 14 | 2011 |
| Phase continuity technique for frequency synthesis M Zanuso, M Elbadry, TP Hung, R Sridhara, F Gatta, J Zhuang US Patent 9,893,875, 2018 | 9 | 2018 |
| Sampling Phase-Locked Loop (PLL) MM Bajestan, MM Izad, M Zanuso US Patent App. 15/957,441, 2019 | 6 | 2019 |
| Multiphase oscillating signal generation and accurate fast frequency estimation M Farazian, S Sayilir, M Zanuso, Y Tang US Patent App. 14/471,530, 2016 | 6 | 2016 |
| An automatic retiming system for asynchronous fractional frequency dividers D Tasca, M Zanuso, S Levantino, C Samori 6th Conference on Ph. D. Research in Microelectronics & Electronics, 1-4, 2010 | 6 | 2010 |
| Local oscillator (LO) phase continuity M Elbadry, M Zanuso, TP Hung, F Gatta, Y Zhu US Patent 10,291,242, 2019 | 5 | 2019 |
| Fast frequency hopping phase locked loop M Zanuso, G Marucci, TP Hung, F Gatta, B Sun US Patent 10,063,366, 2018 | 5 | 2018 |
| A glitch-corrector circuit for low-spur ADPLLs M Zanuso, S Levantino, C Samori, AL Lacaita Analog Integrated Circuits and Signal Processing 73, 201-208, 2012 | 5 | 2012 |
| Phase interpolation-based fractional-N sampling phase-locked loop MM Bajestan, G Marucci, D Park, M Zanuso, Y Tang US Patent 11,411,567, 2022 | 4 | 2022 |
Salvatore LevantinoPolitecnico di Milano在 polimi.it 的电子邮件经过验证
