| Transactional memory with strong atomicity using off-the-shelf memory protection hardware M Abadi, T Harris, M Mehrara Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of …, 2009 | 174 | 2009 |
| Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory M Mehrara, J Hao, PC Hsu, S Mahlke ACM Sigplan Notices 44 (6), 166-176, 2009 | 150 | 2009 |
| Uncovering hidden loop level parallelism in sequential applications H Zhong, M Mehrara, S Lieberman, S Mahlke 2008 IEEE 14th International Symposium on High Performance Computer …, 2008 | 129 | 2008 |
| Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism M Mehrara, PC Hsu, M Samadi, S Mahlke 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 65 | 2011 |
| Adaptive input-aware compilation for graphics engines M Samadi, A Hormati, M Mehrara, J Lee, S Mahlke Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language …, 2012 | 45 | 2012 |
| Multicore compilation strategies and challenges M Mehrara, T Jablin, D Upton, D August, K Hazelwood, S Mahlke IEEE Signal Processing Magazine 26 (6), 55-63, 2009 | 42 | 2009 |
| Low-cost protection for SER upsets and silicon defects M Mehrara, M Attariyan, S Shyam, K Constantinides, V Bertacco, T Austin 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 37 | 2007 |
| Dynamically accelerating client-side web applications through decoupled execution M Mehrara, S Mahlke International Symposium on Code Generation and Optimization (CGO 2011), 74-84, 2011 | 34 | 2011 |
| Customized silicon chips produced using dynamically configurable polymorphic network M Mercaldi-Kim, M Oskin, J Davis, T Austin, M Mehrara US Patent 7,598,766, 2009 | 33 | 2009 |
| Exploiting selective placement for low-cost memory protection M Mehrara, T Austin ACM Transactions on Architecture and Code Optimization (TACO) 5 (3), 1-24, 2008 | 32 | 2008 |
| Compiler-controlled region scheduling for SIMD execution of threads G Diamos, M Mehrara US Patent 9,424,038, 2016 | 27 | 2016 |
| Architectural implications of brick and mortar silicon manufacturing MM Kim, M Mehrara, M Oskin, T Austin Proceedings of the 34th annual international symposium on Computer …, 2007 | 22 | 2007 |
| Cooperative program code transformation DI August, KC Fan, JW Lee, SA Mahlke, M Mehrara US Patent 9,329,846, 2016 | 13 | 2016 |
| Compilation strategies and challenges for multicore signal processing M Mehrara, T Jablin, D Upton, D August, K Hazelwood, S Mahlke IEEE Signal Processing Magazine 26 (6), 55-63, 2009 | 10 | 2009 |
| Technique for grouping instructions into independent strands M Mehrara, M Garland, G Diamos US Patent 9,645,802, 2017 | 8 | 2017 |
| Reliability-aware data placement for partial memory protection in embedded processors M Mehrara, T Austin Proceedings of the 2006 workshop on Memory system performance and …, 2006 | 5 | 2006 |
| Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications M Mehrara University of Michigan, 2011 | 1 | 2011 |
| Register allocation for clustered multi-level register files M Mehrara, G Diamos US Patent 9,229,717, 2016 | | 2016 |
| Architectural Implications of Brick and Mortar Silicon Manufacturing M Mehrara, T Austin, MM Kim, M Oskin | | |
