| Feature Extraction and Identification of Indian Currency Notes S Kamal, S Chawla, N Goel, B Raman Fifth National Conference on Computer Vision, Pattern Recognition, Image …, 2015 | 25 | 2015 |
| FPGA Implementation of an Optimized 8-bit AES Architecture: A Masked S-Box and Pipelined Approach S Chawla, S Aggarwal, S Kamal, N Goel IEEE International Conference on Electronics, Computing and Communication …, 2015 | 20 | 2015 |
| Detection of Sudoku puzzle using image processing and solving by Backtracking, Simulated Annealing and Genetic Algorithms: A comparative analysis S Kamal, SS Chawla, N Goel 2015 Third International Conference on Image Information Processing (ICIIP …, 2015 | 13 | 2015 |
| Design and implementation of a power and speed efficient carry select adder on FPGA SS Chawla, S Aggarwal, N Goel, MS Bhatia 2016 3rd International Conference on Computing for Sustainable Global …, 2016 | 4 | 2016 |
| Identification of Numbers and Positions Using MATLAB to Solve Sudoku on FPGA S Kamal, S Chawla, N Goel 2015 Annual IEEE India Conference (INDICON), 2015 | 4 | 2015 |
| Feature Extraction and Identification of Indian Currency Notes Fifth National Conference on Computer Vision S Kamal, SS Chawla, N Goel, B Raman Pattern Recognition, Image Processing and Graphics (NCVPRIPG), 2015 | 3 | 2015 |
| Design and Analysis of a High Speed Carry Select Adder S Chawla, S Aggarwal, N Goel International Conference on Computing, Communication, Electrical …, 2015 | 2 | 2015 |
| FPGA Implementation of a Traffic Light System: Self Adaptive with Disruptions Indicator S Chawla, S Kamal, N Goel 2015 Annual IEEE India Conference (INDICON), 2015 | 1 | 2015 |
| Comparative Performance Evaluation of Address Decoding Schemes: SRAM Design Perspective A Jain, R Malhotra, R Kaur, A Grover, S Chawla IEEE International Conference on Electronics, Computing and Communication …, 2015 | | 2015 |
| FPGA implementation of an 8-bit AES architecture: A pipelined and masked approach SS Chawla, N Goel IEEE, 2015 | | 2015 |
| FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach SS Chawla, N Goel IEEE, 2015 | | 2015 |
| Chahal, Nidhi 1 Chakraborty, Pavan 526 Chanda, Bhabatosh 73 Chanda, Kunal 17 A Agarwal, N Agnihotri, A Agrawal, W Ahmed, N Ahuja, J Ajmera, ... | | |
Nidhi GoelIndira Gandhi Delhi Technical University for Women在 dce.ac.in 的电子邮件经过验证
Nidhi GoelIndira Gandhi Delhi Technical University for Women在 dce.ac.in 的电子邮件经过验证