| Python as a hardware description language: A case study JI Villar, J Juan, MJ Bellido, J Viejo, D Guerrero, J Decaluwe 2011 VII Southern Conference on Programmable Logic (SPL), 117-122, 2011 | 42 | 2011 |
| Guía para la realización de aplicaciones móviles en los sistemas operativos Android e iOS HC Ávila, J Cortés Monografía de Ingeniería en Telecomunicaciones]. Universidad Distrital …, 2016 | 14 | 2016 |
| Un ejemplo de implemetación de una distribución Linux en un SoC basado en hardware Linux A Muñoz, E Ostúa, P Ruiz, MJ Bellido, J Viejo, A Millan, J Juan, ... Proc. Actas de las IV JCRA, 85-92, 2007 | 14 | 2007 |
| Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements J Viejo, MJ Bellido, A Millán, E Ostúa, J Juan, P Ruiz-de-Clavijo, ... 2006 International Symposium on Industrial Embedded Systems, 1-7, 2006 | 12 | 2006 |
| Design and implementation of a SNTP client on FPGA J Viejo, J Juan, MJ Bellido, E Ostua, A Millan, P Ruiz-de-Clavijo, A Munoz, ... 2008 IEEE International Symposium on Industrial Electronics, 1971-1975, 2008 | 11 | 2008 |
| Digital data processing peripheral design for an embedded application based on the microblaze soft core E Ostua, J Viejo, MJ Bellido, A Millan, J Juan, A Munoz 2008 4th Southern Conference on Programmable Logic, 197-200, 2008 | 10 | 2008 |
| Embedded LUKS (E-LUKS): a hardware solution to IoT security G Cano-Quiveu, P Ruiz-de-clavijo-Vazquez, MJ Bellido, J Juan-Chico, ... Electronics 10 (23), 3036, 2021 | 9 | 2021 |
| Fast hardware implementations of static P systems J Quiros, S Verlan, J Viejo, A Millan, MJ Bellido Computing and Informatics 35 (3), 687-718, 2016 | 8 | 2016 |
| Efficient design of a FFT/IFFT-64 module on ASIC A Millan, MJ Bellido, J Juan, P Ruiz-de Clavijo, D Guerrero, E Ostua, ... Proc. XI Iberchip Workshop (IWS), Salvador de Bahia (Brazil), 305-306, 2005 | 7 | 2005 |
| Minimalistic SDHC-SPI hardware reader module for boot loader applications P Ruiz-de-Clavijo, E Ostúa, MJ Bellido, J Juan, J Viejo, D Guerrero Microelectronics journal 67, 32-37, 2017 | 6 | 2017 |
| Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation J Viejo, J Juan, MJ Bellido, A Millán, P Ruiz-de-Clavijo IEEE Transactions on Instrumentation and Measurement 60 (12), 3961-3963, 2011 | 5 | 2011 |
| Design of a FFT/IFFT module as an IP core suitable for embedded systems J Viejo, A Millán, MJ Bellido, J Juan, P Ruiz-de-Clavijo, D Guerrero, ... 2007 International Symposium on Industrial Embedded Systems, 337-340, 2007 | 5 | 2007 |
| Application of internode model to global power consumption estimation in SCMOS gates A Millán Calderón, MJ Bellido Díaz, J Juan-Chico, P Ruiz de Clavijo, ... International Workshop on Power and Timing Modeling, Optimization and …, 2005 | 5 | 2005 |
| Long-term on-chip verification of systems with logical events scattered in time J Viejo, JI Villar, J Juan, A Millán, E Ostúa, J Quiros Microprocessors and Microsystems 36 (5), 402-408, 2012 | 4 | 2012 |
| Static power consumption in CMOS gates using independent bodies D Guerrero, A Millán, J Juan, MJ Bellido, P Ruiz-de-Clavijo, E Ostúa, ... International Workshop on Power and Timing Modeling, Optimization and …, 2007 | 4 | 2007 |
| Improving the performance of static CMOS gates by using independent bodies D Guerrero, A Millán, J Juan, MJ Bellido, P Ruiz-De-Clavijo, E Ostúa, ... Journal of Low Power Electronics 3 (1), 70-77, 2007 | 4 | 2007 |
| IRIS: An embedded secure boot for IoT devices G Cano-Quiveu, P Ruiz-de-Clavijo-Vazquez, MJ Bellido, J Juan-Chico, ... Internet of Things 23, 100874, 2023 | 3 | 2023 |
| An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation G Cano-Quiveu, P Ruiz-De-Clavijo-Vazquez, MJ Bellido-Diaz, ... IEEE Access 9, 161383-161394, 2021 | 3 | 2021 |
| Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies J Viejo, A Millan, MJ Bellido, E Ostua, P Ruiz-de-Clavijo, A Munoz 2008 4th Southern Conference on Programmable Logic, 7-11, 2008 | 3 | 2008 |
| Logic-level fast current simulation for digital cmos circuits P Ruiz de Clavijo, J Juan-Chico, MJ Bellido Díaz, A Millán Calderón, ... International Workshop on Power and Timing Modeling, Optimization and …, 2005 | 3 | 2005 |
Manuel Jesús BellidoDepartamento de Tecnología Electrónica, Universidad de Sevilla在 us.es 的电子邮件经过验证
