| Ultrahigh density vertical NAND memory device and method of making thereof J Alsmeier, VR Purayath, H Chien, G Matamis, YS Lee, J Kai, Y Zhang US Patent 8,187,936, 2012 | 348 | 2012 |
| Direct observation of negative electron affinity in hydrogen-terminated diamond surfaces D Takeuchi, H Kato, GS Ri, T Yamada, PR Vinod, D Hwang, CE Nebel, ... Applied Physics Letters 86 (15), 2005 | 197 | 2005 |
| Dopant etch selectivity control VR Purayath, A Wang, NK Ingle US Patent 9,263,278, 2016 | 194 | 2016 |
| Air gaps between copper lines VR Purayath, NK Ingle US Patent 9,396,989, 2016 | 190 | 2016 |
| Metal air gap VR Purayath, R Thakur, NK Ingle US Patent 9,159,606, 2015 | 186 | 2015 |
| Metal control gate formation in non-volatile storage JJ Liang, VR Purayath, TW Orimoto US Patent 8,278,203, 2012 | 186 | 2012 |
| Flash gate air gap VR Purayath, NK Ingle US Patent 9,136,273, 2015 | 182 | 2015 |
| Integrated oxide and nitride recess for better channel contact in 3D architectures VR Purayath, R Thakur, NK Ingle US Patent 9,165,786, 2015 | 178 | 2015 |
| Three dimensional NAND device with silicide containing floating gates H Chien, J Alsmeier, G Samachisa, H Chin, G Matamis, Y Zhang, J Kai, ... US Patent 8,928,061, 2015 | 166 | 2015 |
| Integrated bit-line airgap formation and gate stack post clean VR Purayath, R Thakur, S Venkataraman, NK Ingle US Patent 9,496,167, 2016 | 162 | 2016 |
| Integrated oxide recess and floating gate fin trimming VR Purayath, R Thakur, S Venkataraman, NK Ingle US Patent 9,378,978, 2016 | 162 | 2016 |
| Integrated oxide and si etch for 3d cell channel mobility improvements VR Purayath, R Thakur, NK Ingle US Patent App. 14/452,328, 2016 | 132 | 2016 |
| Integrated bit-line airgap formation and gate stack post clean VR Purayath, R Thakur, S Venkataraman, NK Ingle US Patent 9,773,695, 2017 | 131 | 2017 |
| Vertical gate separation J Liu, VR Purayath, X Wang, A Wang, NK Ingle US Patent 9,449,846, 2016 | 131 | 2016 |
| Accommodating imperfectly aligned memory holes VR Purayath US Patent 10,319,739, 2019 | 100 | 2019 |
| Accommodating imperfectly aligned memory holes VR Purayath US Patent 10,325,923, 2019 | 99 | 2019 |
| Charge-trap layer separation and word-line isolation for enhanced 3-D NAND structure VR Purayath, NK Ingle US Patent 9,960,045, 2018 | 99 | 2018 |
| Wordline 3d flash memory air gap VR Purayath, R Thakur, S Venkataraman, NK Ingle US Patent App. 14/452,378, 2016 | 95 | 2016 |
| Method of fabricating non-volatile memory with flat cell structures and air gap isolation VR Purayath, G Matamis, H Chien, J Kai, Y Zhang US Patent 8,946,048, 2015 | 86 | 2015 |
| Methods of fabricating non-volatile memory with air gaps E Harari, T Pham, Y Fong, VR Purayath US Patent 8,546,239, 2013 | 76 | 2013 |
